Atmel Xplained Pro Evaluation Kit ATSAMD20-XPRO ATSAMD20-XPRO Data Sheet

Product codes
ATSAMD20-XPRO
Page of 660
201
Atmel | SMART SAM D20 [DATASHEET]
Atmel-42129K–SAM-D20_datasheet–06/2014
This results in a resolution of 1.0006PPM.
The Sign bit in the Frequency Correction register (FREQCORR.SIGN) determines the direction of the correction. A 
positive value will speed up the frequency, and a negative value will slow down the frequency.
Digital correction also affects the generation of the periodic events from the prescaler. When the correction is applied at 
the end of the correction cycle period, the interval between the previous periodic event and the next occurrence may also 
be shortened or lengthened depending on the correction value.
18.6.5 DMA Operation
Not applicable.
18.6.6 Interrupts
The RTC has the following interrupt sources: 
z
Overflow
z
Compare m
z
Alarm m
z
Synchronization Ready
Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear 
register (INTFLAG) is set when the interrupt condition occurs. Each interrupt can be individually enabled by writing a one 
to the corresponding bit in the Interrupt Enable Set register (INTENSET), and disabled by writing a one to the 
corresponding bit in the Interrupt Enable Clear register (INTENCLR). An interrupt request is generated when the interrupt 
flag is set and the corresponding interrupt is enabled. The interrupt request remains active until the interrupt flag is 
cleared, the interrupt is disabled or the RTC is reset. See INTFLAG for details on how to clear interrupt flags. The RTC 
has one common interrupt request line for all the interrupt sources. The user must read INTFLAG to determine which 
interrupt condition is present.
Note that interrupts must be globally enabled for interrupt requests to be generated. Refer to 
18.6.7 Events
The RTC can generate the following output events, which are generated in the same way as the corresponding 
interrupts:
z
Overflow (OVF)
z
Period n (PERn)
z
Compare n (CMPn)
z
Alarm n (ALARMn)
Output events must be enabled to be generated. Writing a one to an Event Output bit in the Event Control register 
(EVCTRL.xxEO) enables the corresponding output event. Writing a zero to this bit disables the corresponding output 
event. Refer to 
18.6.8 Sleep Mode Operation
The RTC will continue to operate in any sleep mode where the source clock is active. The RTC interrupts can be used to 
wake up the device from a sleep mode, or the RTC events can trigger other operations in the system without exiting the 
sleep mode. 
An interrupt request will be generated after the wake-up if the Interrupt Controller is configured accordingly. Otherwise 
the CPU will wake up directly, without triggering an interrupt. In this case, the CPU will continue executing from the 
instruction following the entry into sleep.
The periodic events can also wake up the CPU through the interrupt function of the Event System. In this case, the event 
must be enabled and connected to an event channel with its interrupt enabled. See 
 for more information.