Atmel Xplained Pro Evaluation Kit ATSAMD20-XPRO ATSAMD20-XPRO Data Sheet
Product codes
ATSAMD20-XPRO
202
Atmel | SMART SAM D20 [DATASHEET]
Atmel-42129K–SAM-D20_datasheet–06/2014
18.6.9 Synchronization
Due to the asynchronicity between CLK_RTC_APB and GCLK_RTC some registers must be synchronized when
accessed. A register can require:
accessed. A register can require:
z
Synchronization when written
z
Synchronization when read
z
Synchronization when written and read
z
No synchronization
When executing an operation that requires synchronization, the Synchronization Busy bit in the Status
register(STATUS.SYNCBUSY) will be set immediately, and cleared when synchronization is complete. The
synchronization Ready interrupt can be used to signal when sync is complete. This can be accessed via the
Synchronization Ready Interrupt Flag in the Interrupt Flag Status and Clear register (INTFLAG.SYNCRDY).
register(STATUS.SYNCBUSY) will be set immediately, and cleared when synchronization is complete. The
synchronization Ready interrupt can be used to signal when sync is complete. This can be accessed via the
Synchronization Ready Interrupt Flag in the Interrupt Flag Status and Clear register (INTFLAG.SYNCRDY).
If an operation that requires synchronization is executed while STATUS.SYNCBUSY is one, the bus will be stalled. All
operations will complete successfully, but the CPU will be stalled and interrupts will be pending as long as the bus is
stalled.
operations will complete successfully, but the CPU will be stalled and interrupts will be pending as long as the bus is
stalled.
The following bits need synchronization when written:
z
Software Reset bit in the Control register (CTRL.SWRST)
z
Enable bit in the Control register (CTRL.ENABLE)
The following registers need synchronization when written:
z
The Counter Value register (COUNT)
z
The Clock Value register (CLOCK)
z
The Counter Period register (PER)
z
The Compare n Value registers (COMPn)
z
The Alarm n Value registers (ALARMn)
z
The Frequency Correction register (FREQCORR)
z
The Alarm n Mask register (MASKn)
Write-synchronization is denoted by the Write-Synchronization property in the register description.
The following registers need synchronization when read:
z
The Counter Value register (COUNT)
z
The Clock Value register (CLOCK)
Read-synchronization is denoted by the Read-Synchronization property in the register description.