Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD Data Sheet

107

SAM4S Series [DATASHEET]

Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14

 

LDR

R8, [R10]

; Loads R8 from the address in R10.

LDRNE

R2, [R5, #960]!

; Loads (conditionally) R2 from a word

; 960 bytes above the address in R5, and

; increments R5 by 960.

STR

R2, [R9,#const-struc]

; const-struc is an expression evaluating

; to a constant in the range 0-4095.

STRH

R3, [R4], #4

; Store R3 as halfword data into address in

; R4, then increment R4 by 4

LDRD

R8, R9, [R3, #0x20]

; Load R8 from a word 32 bytes above the

; address in R3, and load R9 from a word 36

; bytes above the address in R3

STRD

R0, R1, [R8], #-16

; Store R0 to address in R8, and store R1 to

; a word 4 bytes above the address in R8, 

; and then decrement R8 by 16.

Load and Store with register offset.
Syntax

op{type}{cond} Rt, [Rn, Rm {, LSL #n}]

where:
opis one of:
LDRLoad Register.
STRStore Register.
typeis one of:
Bunsigned byte, zero extend to 32 bits on loads.
SBsigned byte, sign extend to 32 bits (LDR only).
Hunsigned halfword, zero extend to 32 bits on loads.
SHsigned halfword, sign extend to 32 bits (LDR only).
-omit, for word.
condis an optional condition code, see 

.

Rtis the register to load or store.
Rnis the register on which the memory address is based.
Rmis a register containing a value to be used as the offset.
LSL #nis an optional shift, with n in the range 0 to 3.
Operation
LDR instructions load a register with a value from memory.
STR instructions store a register value into memory.
The memory address to load from or store to is at an offset from the register Rn. The offset is specified by the 

register Rm and can be shifted left by up to 3 bits using LSL.
The value to load or store can be a byte, halfword, or word. For load instructions, bytes and halfwords can either 

be signed or unsigned. See 

.

Restrictions
In these instructions: