Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD Data Sheet

SAM4S Series [DATASHEET]

Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14

200

NVIC_ISERx [x=0..7]

 Read

/Write

 0x00

0000000

These registers enable interrupts and show which interrupts are enabled.

Write:
0: No effect.
1: Enables the interrupt.
Read:
0: Interrupt disabled.
1: Interrupt enabled.

Notes: 1. If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. 

2. If an interrupt is not enabled, asserting its interrupt signal changes the interrupt state to pending, the NVIC never activates 

the interrupt, regardless of its priority.

31

30

29

28

27

26

25

24

SETENA

23

22

21

20

19

18

17

16

SETENA

15

14

13

12

11

10

9

8

SETENA

7

6

5

4

3

2

1

0

SETENA