Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD Data Sheet

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SAM4S Series [DATASHEET]

Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14

The Reset State Manager asserts the signal exter_nreset to assert the NRST pin. When this occurs, the “nrst_out” 

signal is driven low by the NRST Manager for a time programmed by field ERSTL in the RSTC_MR. This assertion 

duration, named EXTERNAL_RESET_LENGTH, lasts 2

(ERSTL+1)

 Slow Clock cycles. This gives the approximate 

duration of an assertion between 60 µs and 2 seconds. Note that ERSTL at 0 defines a two-cycle duration for the 

NRST pulse.
This feature allows the Reset Controller to shape the NRST pin level, and thus to guarantee that the NRST line is 

driven low for a time compliant with potential external devices connected on the system reset.
As the ERSTL field is in the RSTC_MR, which is backed-up, it can be used to shape the system power-up reset for 

devices requiring a longer startup time than the Slow Clock Oscillator.

The Brownout manager is embedded within the Supply Controller, please refer to the product Supply Controller 

section for a detailed description.

The Reset State Manager handles the different reset sources and generates the internal reset signals. It reports 

the reset status in field RSTTYP of the Status Register (RSTC_SR). The update of the field RSTTYP is performed 

when the processor reset is released.

A general reset occurs when a VDDIO Power-on-reset is detected, a Brownout or a Voltage regulation loss is 

detected by the Supply controller. The vddcore_nreset signal is asserted by the Supply Controller when a general 

reset occurs.
All the reset signals are released and field RSTTYP in the RSTC_SR reports a General Reset. As the RSTC_MR 

is reset, the NRST line rises two cycles after the vddcore_nreset, as ERSTL defaults at value 0x0.

 shows how the General Reset affects the reset signals.

SLCK

periph_nreset

proc_nreset

NRST

(nrst_out)

EXTERNAL RESET LENGTH

= 2 cycles 

MCK

Processor Startup

= 2 cycles

vddbu_nreset

Any

Freq.

RSTTYP

XXX

0x0 = General Reset

XXX