Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD Data Sheet

SAM4S Series [DATASHEET]

Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14

338

SUPC_SMMR

0x400E1414

Read/Write

This register is located in the VDDIO domain.
This register can only be written if the WPEN bit is cleared in the System Controller Write Protection Mode Register 

(SYSC_MR). 



Selects the threshold voltage of the supply monitor. Refer to the electrical characteristics for voltage values.





0 (NOT_ENABLE): The core reset signal “vddcore_nreset” is not affected when a supply monitor detection occurs.
1 (ENABLE): The core reset signal, vddcore_nreset is asserted when a supply monitor detection occurs.



0 (NOT_ENABLE): The SUPC interrupt signal is not affected when a supply monitor detection occurs.
1 (ENABLE): The SUPC interrupt signal is asserted when a supply monitor detection occurs.

31

30

29

28

27

26

25

24

–

–

–

–

–

–

–

–

23

22

21

20

19

18

17

16

–

–

–

–

–

–

–

–

15

14

13

12

11

10

9

8

–

–

SMIEN

SMRSTEN

–

SMSMPL

7

6

5

4

3

2

1

0

–

–

–

–

SMTH

0x0

SMD

Supply Monitor disabled

0x1

CSM

Continuous Supply Monitor 

0x2

32SLCK

Supply Monitor enabled one SLCK period every 32 SLCK periods

0x3

256SLCK

Supply Monitor enabled one SLCK period every 256 SLCK periods

0x4

2048SLCK

Supply Monitor enabled one SLCK period every 2,048 SLCK periods