Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD Data Sheet

SAM4S Series [DATASHEET]

Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14

340

SUPC_WUMR

0x400E141C

Read/Write 

This register is located in the VDDIO domain.
This register can only be written if the WPEN bit is cleared in the System Controller Write Protection Mode Register 

(SYSC_MR). 



0 (NOT_ENABLE): The supply monitor detection has no wake-up effect.
1 (ENABLE): The supply monitor detection forces the wake-up of the core power supply.



0 (NOT_ENABLE): The RTT alarm signal has no wake-up effect.
1 (ENABLE): The RTT alarm signal forces the wake-up of the core power supply.



0 (NOT_ENABLE): The RTC alarm signal has no wake-up effect.
1 (ENABLE): The RTC alarm signal forces the wake-up of the core power supply.



0 (NOT_ENABLE): The WKUP0 input pin is not connected with low-power debouncer.
1 (ENABLE): The WKUP0 input pin is connected with low-power debouncer and forces a system wake-up.



0 (NOT_ENABLE): The WKUP1 input pin is not connected with low-power debouncer.
1 (ENABLE): The WKUP1 input pin is connected with low-power debouncer and forces a system wake-up.



0 (NOT_ENABLE): A low-power debounce event does not create an immediate clear on the first half of GPBR registers.
1 (ENABLE): A low-power debounce event on WKUP0 or WKUP1 generates an immediate clear on the first half of GPBR 

registers. 

31

30

29

28

27

26

25

24

–

–

–

–

–

–

–

–

23

22

21

20

19

18

17

16

–

–

–

–

–

LPDBC

15

14

13

12

11

10

9

8

–

WKUPDBC

–

–

–

–

7

6

5

4

3

2

1

0

LPDBCCLR

LPDBCEN1

LPDBCEN0

–

RTCEN

RTTEN

SMEN

–