Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD Data Sheet
Product codes
ATSAM4S-WPIR-RD
SAM4S Series [DATASHEET]
Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14
352
Figure 20-3.
Code Read Optimization for FWS = 3
Note: When FWS is included between 1 and 3, in case of sequential reads, the first access takes (FWS+1) cycles, the other ones only
1 cycle.
20.4.2.3 Code Loop Optimization
Code loop optimization is enabled when the CLOE bit of EEFC_FMR is set to 1.
When a backward jump is inserted in the code, the pipeline of the sequential optimization is broken and becomes
When a backward jump is inserted in the code, the pipeline of the sequential optimization is broken and becomes
inefficient. In this case, the loop code read optimization takes over from the sequential code read optimization to
prevent the insertion of wait states. The loop code read optimization is enabled by default. In EEFC_FMR, if the bit
CLOE is reset to 0 or the bit SCOD is set to 1, these buffers are disabled and the loop code read is not optimized.
When code loop optimization is enabled, if inner loop body instructions L
When code loop optimization is enabled, if inner loop body instructions L
0
to L
n
are positioned from the 128-bit
Flash memory cell M
b0
to the memory cell M
p1
, after recognition of a first backward branch, the first two Flash
memory cells M
b0
and M
b1
targeted by this branch are cached for fast access from the processor at the next loop
iteration.
Then by combining the sequential prefetch (described in
Then by combining the sequential prefetch (described in
) through the
loop body with the fast read access to the loop entry cache, the entire loop can be iterated with no wait state.
illustrates code loop optimization.
Figure 20-4.
Code Loop Optimization
Flash Access
Buffer 0 (128bits)
Master Clock
ARM Request
(32-bit)
Data To ARM
Buffer 1 (128bits)
0-3
XXX
XXX
Bytes 16-31
@Byte 0
@4
@8
Bytes 0-15
Bytes 16-31
Bytes 32-47
Bytes 48-63
XXX
Bytes 0-15
4-7
8-11
12-15
@12
@16
@20
24-27
28-31
32-35
36-39
16-19
20-23
40-43
44-47
@24
@28 @32
@36
@40
@44
@48
@52
Bytes 32-47
48-51
L
n
L
n-1
L
n-2
L
n-3
L
n-4
L
n-5
L
5
L
4
L
3
L
2
L
1
L
0
B
1
B
2
B
3
B
4
B
5
B
6
B
7
B
0
P
1
P
2
P
3
P
4
P
5
P
6
P
7
P
0
M
b0
M
b0
M
b1
M
p0
M
p1
Backward address jump
2x128-bit loop entry
cache
2x128-bit prefetch
buffer
L
0
Loop Entry instruction
L
n
Loop End instruction
Flash Memory
128-bit words
M
b0
Branch Cache 0
M
b1
Branch Cache 1
M
p0
Prefetch Buffer 0
M
p1
Prefetch Buffer 1