Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD Data Sheet
Product codes
ATSAM4S-WPIR-RD
353
SAM4S Series [DATASHEET]
Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14
20.4.2.4 Data Read Optimization
The organization of the Flash in 128 bits (or 64 bits) is associated with two 128-bit (or 64-bit) prefetch buffers and
one 128-bit (or 64-bit) data read buffer, thus providing maximum system performance. This buffer is added in order
to store the requested data plus all the data contained in the 128-bit (64-bit) aligned data. This speeds up
). The data read optimization is enabled
by default. If the SCOD bit in EEFC_FMR is set to 1, this buffer is disabled and the data read is no longer
optimized.
Note:
No consecutive data read accesses are mandatory to benefit from this optimization.
Figure 20-5.
Data Read Optimization for FWS = 1
Flash Access
Buffer (128bits)
Master Clock
ARM Request
(32-bit)
XXX
Data To ARM
Bytes 0-15
Bytes 16-31
Bytes 0-15
Bytes 0-3
4-7
8-11
12-15
16-19
20-23
XXX
Bytes 16-31
@Byte 0
@ 4
@ 8
@ 12
@ 16
@ 20
@ 24
@ 28
@ 32
@ 36
XXX
Bytes 32-47
24-27
28-31
32-35