Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD Data Sheet

SAM4S Series [DATASHEET]

Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14

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The Bus Matrix implements a multi-layer AHB that enables parallel access paths between multiple AHB masters 

and slaves in a system, thus increasing overall bandwidth. The Bus Matrix interconnects AHB masters to AHB 

slaves. The normal latency to connect a master to a slave is one cycle. The exception is the default master of the 

accessed slave which is connected directly (zero cycle latency). 
The Bus Matrix user interface also provides a System I/O Configuration user interface with registers that support 

application-specific features.

The Bus Matrix manages the masters listed in 

. Each master can perform an access to an available 

slave concurrently with other masters.
Each master has its own specifically-defined decoder. To simplify addressing, all the masters have the same 

decoding.

The Bus Matrix manages the slaves listed in 

. Each slave has its own arbiter providing a different 

arbitration per slave.  

Master 0

Cortex-M4 Instruction/Data

Master 1

Cortex-M4 System 

Master 2

Peripheral DMA Controller (PDC)

Master 3

CRC Calculation Unit

Slave 0

Internal SRAM

Slave 1

Internal ROM

Slave 2

Internal Flash

Slave 3

External Bus Interface

Slave 4

Peripheral Bridge