Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD Data Sheet

Product codes
ATSAM4S-WPIR-RD
Page of 1231
427
SAM4S Series [DATASHEET]
Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14
25.2.3 Master to Slave Access
 gives valid paths for master to slave access on Matrix 0. The paths shown as “-” are forbidden or not 
wired, e.g. access from the Cortex-M4 S Bus to the internal ROM. 
25.3
Memory Mapping
The Bus Matrix provides one decoder for every AHB master interface. The decoder offers each AHB master 
several memory mappings. In fact, depending on the product, each memory area may be assigned to several 
slaves. Thus it is possible to boot at the same address while using different AHB slaves.
25.4
Special Bus Granting Techniques
The Bus Matrix provides some speculative bus granting techniques in order to anticipate access requests from 
some masters. This technique reduces latency at the first access of a burst or single transfer. Bus granting sets a 
default master for every slave. 
At the end of the current access, if no other request is pending, the slave remains connected to its associated 
default master. A slave can be associated with one of the three implementations of default masters: 
No default master
Last access master
Fixed default master
25.4.1 No Default Master
At the end of the current access, if no other request is pending, the slave is disconnected from all masters. No 
default master suits low-power mode.
25.4.2 Last Access Master
At the end of the current access, if no other request is pending, the slave remains connected to the last master that 
performed an access request.
25.4.3 Fixed Default Master
At the end of the current access, if no other request is pending, the slave connects to its fixed default master. 
Unlike the last access master, the fixed master does not change unless the user modifies it by software (field 
FIXED_DEFMSTR of the related MATRIX_SCFG).
To change from one kind of default master to another, the Bus Matrix user interface provides the Slave 
Configuration registers (MATRIX_SCFGx), one for each slave, used to set a default master for each slave. 
MATRIX_SCFGx contains the fields DEFMSTR_TYPE and FIXED_DEFMSTR. The 2-bit DEFMSTR_TYPE field 
Table 25-3.
 Master to Slave Access
Slaves
Masters
0 1
 
2
3
Cortex-M4 I/D Bus
Cortex-M4 S Bus
PDC
CRCCU
0
Internal SRAM
X
X
X
1
Internal ROM
X
X
X
2
Internal Flash
X
-
X
3
External Bus Interface
X
X
X
4
 Peripheral Bridge
X
X