Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD Data Sheet

SAM4S Series [DATASHEET]

Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14

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selects the default master type (no default, last access master, fixed default master) whereas the 4-bit 

FIXED_DEFMSTR field selects a fixed default master, provided that DEFMSTR_TYPE is set to fixed default 

master. Refer to 

The Bus Matrix provides an arbitration technique that reduces latency when conflicting cases occur; for example, 

when two or more masters try to access the same slave at the same time. One arbiter per AHB slave is provided to 

arbitrate each slave differently.
The Bus Matrix provides the user with two arbitration types for each slave:

1. Round-robin arbitration (default)

2. Fixed priority arbitration

The field ARBT of MATRIX_SCFG is used to select the type of arbitration.
Each algorithm may be complemented by selecting a default master configuration for each slave.
In case of re-arbitration, specific conditions apply. See 

.

Each arbiter has the ability to arbitrate between requests of two or more masters. To avoid burst breaking and to 

provide the maximum throughput for slave interfaces, arbitration should take place during the following cycles:

1. Idle cycles: When a slave is not connected to any master or is connected to a master which is not currently 

accessing it.

2. Single cycles: When a slave is performing a single access.
3. End of burst cycles: When the current cycle is the last cycle of a burst transfer. For a defined burst length, 

predicted end of burst matches the size of the transfer but is managed differently for undefined burst length. 

4. Slot cycle limit: When the slot cycle counter has reached the limit indicating that the current master access is 

too long and must be broken. See 

In order to prevent slave handling during undefined length bursts (INCR), the Bus Matrix provides specific logic to 

re-arbitrate before the end of the INCR transfer.
A predicted end of burst is used for defined length burst transfer, which is selected between the following:

1. Infinite: No predicted end of burst is generated and therefore INCR burst transfer will never be broken.

2.  Four-beat bursts: Predicted end of burst is generated at the end of each four beat boundary inside INCR 

transfer.

3. Eight-beat bursts: Predicted end of burst is generated at the end of each eight beat boundary inside INCR 

transfer.

4. Sixteen-beat bursts: Predicted end of burst is generated at the end of each sixteen beat boundary inside 

INCR transfer.

This selection can be done through the field ULBT of the Master Configuration Registers (MATRIX_MCFG).

The Bus Matrix contains specific logic to break accesses that are too long, such as very long bursts on a very slow 

slave (e.g. an external low-speed memory). At the beginning of the burst access, a counter is loaded with the value 

previously written in the SLOT_CYCLE field of the related MATRIX_SCFG and decreased at each clock cycle. 

When the counter reaches zero, the arbiter has the ability to re-arbitrate at the end of the current byte, half-word or 

word transfer.