Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD Data Sheet

429

SAM4S Series [DATASHEET]

Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14

Bus Matrix arbiters use the round-robin algorithm to dispatch the requests from different masters to the same 

slave. If two or more masters make a request at the same time, the master with the lowest number is serviced first. 

The others are then serviced in a round-robin manner.
Three round-robin algorithms are implemented:



Round-Robin arbitration without default master



Round-Robin arbitration with last access master



Round-Robin arbitration with fixed default master

Round-robin arbitration without default master is the main algorithm used by Bus Matrix arbiters. It allows the Bus 

Matrix to dispatch requests from different masters to the same slave in a pure round-robin manner. At the end of 

the current access, if no other request is pending, the slave is disconnected from all masters. This configuration 

incurs one latency cycle for the first access of a burst. Arbitration without default master can be used for masters 

that perform significant bursts.

Round-robin arbitration with last access master is a biased round-robin algorithm used by Bus Matrix arbiters. It 

allows the Bus Matrix to remove the one latency cycle for the last master that accessed the slave. At the end of the 

current transfer, if no other master request is pending, the slave remains connected to the last master that 

performs the access. Other non-privileged masters incur one latency cycle if they want to access the same slave. 

This technique can be used for masters that mainly perform single accesses.

Round-robin arbitration with fixed default master is an algorithm used by the Bus Matrix arbiters to remove the one 

latency cycle for the fixed default master per slave. At the end of the current access, the slave remains connected 

to its fixed default master. Every request attempted by the fixed default master does not incur latency, whereas 

other non-privileged masters still incur one latency cycle. This technique can be used for masters that mainly 

perform single accesses.

The fixed priority arbitration algorithm is used by the Bus Matrix arbiters to dispatch the requests from different 

masters to the same slave by using the fixed priority defined by the user. If requests from two or more masters are 

active at the same time, the master with the highest priority is serviced first. If requests from two or more masters 

with the same priority are active at the same time, the master with the highest number is serviced first.
For each slave, the priority of each master may be defined through the Priority registers for slaves 

(MATRIX_PRAS and MATRIX_PRBS).

The System I/O Configuration register (CCFG_SYSIO) configures I/O lines in system I/O mode (such as JTAG, 

ERASE, USB, etc.) or as general-purpose I/O lines. Enabling or disabling the corresponding I/O lines in peripheral 

mode or in PIO mode (PIO_PER or PIO_PDR registers) in the PIO controller has no effect. However, the direction 

(input or output), pull-up, pull-down and other mode control is still managed by the PIO controller.