Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD Data Sheet
Product codes
ATSAM4S-WPIR-RD
SAM4S Series [DATASHEET]
Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14
450
NCS_WR_HOLD = NWE_CYCLE - NCS_WR_SETUP - NCS_WR_PULSE
26.8.3.4 Null Delay Setup and Hold
If null setup parameters are programmed for NWE and/or NCS, NWE and/or NCS remain active continuously in
case of consecutive write cycles in the same memory (see
). However, for devices that perform write
operations on the rising edge of NWE or NCS, such as SRAM, either a setup or a hold must be programmed.
Figure 26-10. Null Setup and Hold Values of NCS and NWE in Write Cycle
26.8.3.5 Null Pulse
Programming null pulse is not permitted. Pulse must be at least set to 1. A null value leads to unpredictable
behavior.
26.8.4 Write Mode
The WRITE_MODE parameter in the SMC_MODE register of the corresponding chip select indicates which signal
controls the write operation.
26.8.4.1 Write is Controlled by NWE (WRITE_MODE = 1):
shows the waveforms of a write operation with WRITE_MODE set to 1. The data is put on the bus
during the pulse and hold steps of the NWE signal. The internal data buffers are switched to output mode after the
NWE_SETUP time, and until the end of the write cycle, regardless of the programmed waveform on NCS.
NCS
MCK
NWE
D[7:0]
NWE_PULSE
NCS_WR_PULSE
NWE_CYCLE
NWE_PULSE
NCS_WR_PULSE
NWE_CYCLE
NWE_PULSE
NCS_WR_PULSE
NWE_CYCLE
A[23:0]