Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD Data Sheet
Product codes
ATSAM4S-WPIR-RD
933
SAM4S Series [DATASHEET]
Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14
39.6
Functional Description
The PWM macrocell is primarily composed of a clock generator module and
4
channels.
Clocked by the master clock (MCK), the clock generator module provides 13 clocks.
Each channel can independently choose one of the clock generator outputs.
Each channel generates an output waveform with attributes that can be defined independently for each
channel through the user interface registers.
39.6.1 PWM Clock Generator
Figure 39-2.
Functional View of the Clock Generator Block Diagram
The PWM master clock (MCK) is divided in the clock generator module to provide different clocks available for all
channels. Each channel can independently select one of the divided clocks.
The clock generator is divided in three blocks:
The clock generator is divided in three blocks:
̶
a modulo n counter which provides 11 clocks: f
MCK
, f
MCK
/2, f
MCK
/4, f
MCK
/8, f
MCK
/16, f
MCK
/32, f
MCK
/64,
f
MCK
/128, f
MCK
/256, f
MCK
/512, f
MCK
/1024
̶
two linear dividers (1, 1/2, 1/3, ... 1/255) that provide two separate clocks: clkA and clkB
Each linear divider can independently divide one of the clocks of the modulo n counter. The selection of the clock
to be divided is made according to the PREA (PREB) field of the PWM Clock register (PWM_CLK). The resulting
clock clkA (clkB) is the clock selected divided by DIVA (DIVB) field value.
modulo n counter
MCK/2
MCK/4
MCK/4
MCK/16
MCK/32
MCK/64
MCK/32
MCK/64
MCK/8
Divider A
clkA
DIVA
PWM_MR
MCK
MCK/128
MCK/256
MCK/512
MCK/1024
MCK/256
MCK/512
MCK/1024
PREA
Divider B
clkB
DIVB
PWM_MR
PREB
MCK