Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD Data Sheet
Product codes
ATSAM4S-WPIR-RD
935
SAM4S Series [DATASHEET]
Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14
An asynchronous fault protection mechanism that has the highest priority to override the two complementary
outputs (PWMHx/PWMLx) in case of fault detection (outputs forced to ‘0’, ‘1’).
39.6.2.2 Comparator
The comparator continuously compares its counter value with the channel period defined by CPRD in the
(PWM_CPRDx) and the duty-cycle defined by CDTY in the
(PWM_CDTYx) to generate an output signal OCx accordingly.
The different properties of the waveform of the output OCx are:
the clock selection. The channel counter is clocked by one of the clocks provided by the clock generator
described in the previous section. This channel parameter is defined in the CPRE field of the
(PWM_CMRx). This field is reset at ‘0’.
the waveform period. This channel parameter is defined in the CPRD field of the PWM_CPRDx register.
If the waveform is left aligned, then the output waveform period depends on the counter source clock and
can be calculated:
By using the PWM master clock (MCK) divided by an X given prescaler value (with X being 1, 2, 4, 8, 16, 32,
64, 128, 256, 512, or 1024), the resulting period formula will be:
By using the PWM master clock (MCK) divided by one of both DIVA or DIVB divider, the formula becomes,
respectively:
or
If the waveform is center aligned then the output waveform period depends on the counter source clock and
can be calculated:
By using the PWM master clock (MCK) divided by an X given prescaler value
(with X being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024). The resulting period formula will be:
By using the PWM master clock (MCK) divided by one of both DIVA or DIVB divider, the formula becomes,
respectively:
or
the waveform duty-cycle. This channel parameter is defined in the CDTY field of the PWM_CDTYx
register.
If the waveform is left aligned then:
If the waveform is center aligned, then:
X
CPRD
×
(
)
MCK
-------------------------------
X
C
× RPD DIVA
×
(
)
MCK
----------------------------------------------------
X
C
× RPD DIVB
×
(
)
MCK
----------------------------------------------------
2
X
CPRD
×
×
(
)
MCK
----------------------------------------
2
X
C
× PRD DIVA
×
×
(
)
MCK
-------------------------------------------------------------
2
X
C
× PRD
×
DIVB
×
(
)
MCK
-------------------------------------------------------------
duty cycle
period
1 fchannel_x_clock
CDTY
×
⁄
–
(
)
period
----------------------------------------------------------------------------------------------------
=
duty cycle
period 2
⁄
(
) 1 fchannel_x_clock CDTY
×
⁄
–
(
) )
period 2
⁄
(
)
-------------------------------------------------------------------------------------------------------------------
=