Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD Data Sheet
Product codes
ATSAM4S-WPIR-RD
SAM4S Series [DATASHEET]
Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14
934
After a reset of the PWM controller, DIVA (DIVB) and PREA (PREB) are set to ‘0’. This implies that after reset clkA
(clkB) are turned off.
At reset, all clocks provided by the modulo n counter are turned off except clock “MCK”. This situation is also true
At reset, all clocks provided by the modulo n counter are turned off except clock “MCK”. This situation is also true
when the PWM master clock is turned off through the Power Management Controller.
CAUTION
:
Before using the PWM macrocell, the programmer must first enable the PWM clock in the Power
Management Controller (PMC).
39.6.2 PWM Channel
39.6.2.1 Channel Block Diagram
Figure 39-3.
Functional View of the Channel Block Diagram
Each of the 4 channels is composed of six blocks:
A clock selector which selects one of the clocks provided by the clock generator (described in
).
A counter clocked by the output of the clock selector. This counter is incremented or decremented according
to the channel configuration and comparators matches. The size of the counter is 16 bits.
A comparator used to compute the OCx output waveform according to the counter value and the
configuration. The counter value can be the one of the channel counter or the one of the channel 0 counter
according to SYNCx bit in the
(PWM_SCM).
A 2-bit configurable gray counter enables the stepper motor driver. One gray counter drives 2 channels.
A dead-time generator providing two complementary outputs (DTOHx/DTOLx) which allows to drive external
power control switches safely.
An output override block that can force the two complementary outputs to a programmed value
(OOOHx/OOOLx).
Comparator
x
Clock
Selector
Channel x
Dead-Time
Generator
Output
Override
OCx
DTOHx
DTOLx
Fault
Protection
OOOHx
PWMHx
PWMLx
OOOLx
Counter
Channel x
Duty-Cycle
Period
Update
Counter
Channel 0
MUX
SYNCx
Dead-Time
Generator
Output
Override
OCy
DTOHy
DTOLy
Fault
Protection
OOOHy
PWMHy
PWMLy
OOOLy
Channel y (= x+1)
MUX
MU
X
2-bit gray
counter z
Comparator
y
from
Clock
Generator
from APB
Peripheral Bus
z = 0 (x = 0, y = 1),
z = 1 (x = 2, y = 3),
z = 2 (x = 4, y = 5),
z = 3 (x = 6, y = 7)
z = 1 (x = 2, y = 3),
z = 2 (x = 4, y = 5),
z = 3 (x = 6, y = 7)