Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Data Sheet
Product codes
ATSAMD21-XPRO
261
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181C–SAM-D21_Datasheet–07/2014
19.
DMAC – Direct Memory Access Controller
19.1 Overview
The Direct Memory Access Controller (DMAC) contains both a Direct Memory Access engine and a Cyclic Redundancy
Check (CRC) engine. The DMAC can transfer data between memories and peripherals, and thus off-load these tasks
from the CPU. It enables high data transfer rates with minimum CPU intervention, and frees up CPU time. With access to
all peripherals, the DMAC can handle automatic transfer of data between communication modules.
Check (CRC) engine. The DMAC can transfer data between memories and peripherals, and thus off-load these tasks
from the CPU. It enables high data transfer rates with minimum CPU intervention, and frees up CPU time. With access to
all peripherals, the DMAC can handle automatic transfer of data between communication modules.
For the DMA part of the DMAC, it has several DMA channels which all can receive different types of transfer triggers,
which will result in transfer requests from the DMA channels to the arbiter. Refer to
which will result in transfer requests from the DMA channels to the arbiter. Refer to
. The arbiter will grant one
DMA channel at a time to act as the active channel. When the active channel has been granted, the fetch engine of the
DMAC will fetch a transfer descriptor from SRAM into the internal memory of the active channel, before the active
channel starts its data transmission. A DMA channel's data transfer can be interrupted by a higher prioritized channel.
The DMAC will write back the updated transfer descriptor from the internal memory of the active channel to SRAM,
before the higher prioritized channel gets to start its transfer. Once a DMA channel is done with its transfer optionally
interrupts and events can be generated.
DMAC will fetch a transfer descriptor from SRAM into the internal memory of the active channel, before the active
channel starts its data transmission. A DMA channel's data transfer can be interrupted by a higher prioritized channel.
The DMAC will write back the updated transfer descriptor from the internal memory of the active channel to SRAM,
before the higher prioritized channel gets to start its transfer. Once a DMA channel is done with its transfer optionally
interrupts and events can be generated.
As one can see from
, the DMAC has four bus interfaces. The data transfer bus, which is used for performing
the actual DMA transfer is an AHB master interface. The AHB/APB Bridge bus is an APB slave interface and is the bus
used when writing and reading the I/O registers of the DMAC. The descriptor fetch bus is an AHB master interface and is
used by the fetch engine, to fetch transfer descriptors from SRAM before a transfer can be started or continued. At last
there is the write-back bus, which is an AHB master interface and it is used to write the transfer descriptor back to SRAM.
used when writing and reading the I/O registers of the DMAC. The descriptor fetch bus is an AHB master interface and is
used by the fetch engine, to fetch transfer descriptors from SRAM before a transfer can be started or continued. At last
there is the write-back bus, which is an AHB master interface and it is used to write the transfer descriptor back to SRAM.
As mentioned, the DMAC also has a CRC module available. This can be used by software to detect an accidental error
in the transferred data and to take corrective action, such as requesting the data to be sent again or simply not using the
incorrect data.
in the transferred data and to take corrective action, such as requesting the data to be sent again or simply not using the
incorrect data.
19.2 Features
z
Data transfer between
z
Peripheral to peripheral
z
Peripheral to memory
z
Memory to peripheral
z
Memory to memory
z
Transfer trigger sources
z
Software
z
Events from Event System
z
Dedicated requests from peripherals
z
SRAM based transfer descriptors
z
Single transfer using one descriptor
z
Multi-buffer or circular buffer modes by linking multiple descriptors
z
12 channels
z
Enable
12
independent transfers
z
Automatic descriptor fetch for each channel
z
Suspend/resume operation support for each channel
z
Flexible arbitration scheme
z
4 configurable priority levels for each channel
z
Fixed or round-robin priority scheme within each priority level
z
From 1 to 256kB data transfer in a single block transfer
z
Multiple addressing modes
z
Static
z
Configurable increment scheme