Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Data Sheet
Product codes
ATSAMD21-XPRO
262
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181C–SAM-D21_Datasheet–07/2014
z
Optional interrupt generation
z
On block transfer complete
z
On error detection
z
On channel suspend
z
4 event inputs
z
One event input for each of the
4 least significant DMA
channels
z
Can be selected to trigger normal transfers, periodic transfers or conditional transfers
z
Can be selected to suspend or resume channel operation
z
4 event outputs
z
One output event for each of the
4 least significant DMA channels
z
Selectable generation on AHB, burst, block or transaction transfer complete
z
Error management supported by write-back function
z
Dedicated Write-Back memory section for each channel to store ongoing descriptor transfer
z
CRC polynomial software selectable to
z
CRC-16 (CRC-CCITT)
z
CRC-32 (IEEE 802.3)
19.3 Block Diagram
Figure 19-1. DMAC Block Diagram
19.4 Signal Description
Not applicable.
19.5 Product Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
HIGH SPEED
BUS MATRIX
BUS MATRIX
AHB/APB
Bridge
CPU
SRAM
S
S
M
M
Events
Channel 0
Channel 1
Channel n
Arbiter
DMA Channels
MASTER
Active
Channel
CRC
Engine
Fetch
Engine
Interrupt /
Events
DMAC
Interrupts
Transfer
Triggers
Triggers
n
Data Transfer
Write-back
Descriptor Fetch