Intel E3815 FH8065301567411 Data Sheet

Product codes
FH8065301567411
Page of 5308
Intel
®
 Atom™ Processor E3800 Product Family
1036
Datasheet
14.13.4
FCR (FCR_CGA_Write)—Offset 3DAh
Feature Control
Access Method
Default: 00h
Bit 
Range
Default & 
Access
Field Name (ID): Description
7:0
0b
WO
PALETTE_READ_INDEX: 
The 8-bit index value programmed into this register chooses 
which of 256 standard color data positions within the palette are to be made accessible 
for being read from via the Palette Data Register (DACDATA). The index value held in 
this register is automatically incremented when all three bytes of the color data position 
selected by the current index have been read. A write to this register will abort a 
uncompleted palette write sequence. This register allows access to the palette even 
when running non-VGA display modes.
Type: 
Memory Mapped I/O Register
(Size: 8 bits)
Offset: 
GTTMMADR_LSB Type: 
PCI Configuration Register (Size: 32 
bits)
GTTMMADR_LSB Reference: 
[B:0, D:2, F:0] + 10h
7
4
0
0
0
0
0
0
0
0
0
RE
SERV
ED
V
S
Y
N
C_C
O
NTRO
L
RE
SE
RVED_1
Bit 
Range
Default & 
Access
Field Name (ID): Description
7:4
0b
RW
RESERVED: 
Read as 0.
3
0b
RW
VSYNC_CONTROL: 
This bit is provided for compatibility only and has no other 
function. Reads and writes to this bit have no effect other than to change the value of 
this bit. The previous definition of this bit selected the output on the VSYNC pin. 
0 = Was used to set VSYNC out put on the VSYNC pin (default).  
1 = Was used to set the log i cal 'OR' of VSYNC and Display Ena ble output on the 
VSYNC pin. This capability was not typically very useful.. 
2:0
0b
RW
RESERVED_1: 
Read as 0.