Intel E3815 FH8065301567411 Data Sheet

 

Intel

®

 Atom™ Processor E3800 Product Family

Datasheet

1035

Palette Read Index Register

Default: 00h

3:2

0b

RW

These bits can select the dot clock source for the CRT interface. The 

bits should be used to select the dot clock in standard native VGA modes only. When in 

the centering or upper left corner modes, these bits should be set to have no effect on 

the clock rate. The actual frequencies that these bits select, if they have any affect at 

all, is programmable through the DPLL registers that default to the standard values used 

for VGA. 

00 = CLK0, 25.175 MHz (for standard VGA modes with 640 pixel (8-dot) horizontal 

resolution) (default) 

01 = CLK1, 28.322 MHz. (for standard VGA modes with 720 pixel (9-dot) horizontal 

resolution) 

10 = Was used to select an external clock (now unused) 

11 = Reserved

1

0b

RW

VGA Compatibility bit enables access 

to local video memory (frame buffer) at A0000(BFFFFh. When disabled, accesses to VGA 

memory are blocked in this region. This bit is independent of and does not block CPU 

access to the video linear frame buffer at other addresses. Note that it is typical for AGP 

chipsets to shadow this register to allow proper steering of memory accesses to the 

proper bus. 

0 = Prevent CPU access to memory/registers/ROM through the A0000-BFFFF VGA 

memory aperture (default).  

1 = Allow CPU access to memory/registers/ROM through the A0000-BFFFF VGA memory 

aperture. This memory must be mapped as UC by the CPU; see VGA Host Access 

Memory Munging in Display and Overlay Functions.

0

0b

RW

This bit selects 3Bxh or 3Dxh as the I/O address for the CRT 

Controller re gisters, the Feature Control Register (FCR), and Input Status Register 1 

(ST01). Presently ignored (whole range is claimed), but will ignore 3Bx for color 

configuration or 3Dx for monochrome. Note that it is typical in AGP chipsets to shadow 

this bit and properly steer I/O cycles to the proper bus for operation where a MDA exists 

on another bus such as ISA. 

0 = Select 3Bxh I/O address (MDA emulation) (default).  

1 = Select 3Dxh I/O address (CGA emulation). 

Memory Mapped I/O Register

(Size: 8 bits)

PCI Configuration Register (Size: 32 

bits)
GTTMMADR_LSB Reference: 

[B:0, D:2, F:0] + 10h

7

4

0

0

0

0

0

0

0

0

0

PA

LET

T

E_REA

D

_INDEX