Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
1135
15.8.20
reg_gpd_gp_reg_reg_gp_srst_type
(gpd_gp_reg_reg_gp_srst)—Offset 4Ch
Soft reset for several modules in the system. If '1' is written to a bit, the module(s)
connected to that bit are held in reset until a '0' is written to that bit.
Access Method
Default: 00000000h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
unus
ed
_re
g
_gp
_
switch_g
dc
2
re
g_gp
_sw
itch_g
d
c2
Bit
Range
Default &
Access
Description
31:1
0h
RW
unused_reg_gp_switch_gdc2:
Unused
0
0h
RW
reg_gp_switch_gdc2:
Selects the control stream switch for the GDC2. GDC2 can be
controlled by the scalar processor (value=1) or the ISP (value=0)
Type:
Memory Mapped I/O Register
(Size: 32 bits)
ISPMMADR Type:
PCI Configuration Register (Size: 32 bits)
ISPMMADR Reference:
[B:0, D:3, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
unu
sed
_
re
g_gp
_srs
t
SRS
T
_WBUS
SRST_HOST
12BU
S
SRS
T
_NBUS
SR
ST_OC
P2CIO
SRST
_SP
SRST_SF_G
D
C
2_CELLS
SRST_SF_G
D
C
1_CELLS
SRST
_SF_DMA_C
E
LLS
SRST
_S
F_ISYS
_SP
SRST_SF_MC_SP
SR
S
T
_S
F_
SIF
_
S
P
S
R
ST_SF
_
PIF_CELLS
SRST_S
F_ISP
_
SP
SRST_D
MA
SRST_SL
V
_GRP_BU
S
SRS
T
_ISP
SRST_VEC_BU
S
SR
S
T
_GD
C
2
SR
S
T
_GD
C
1
SRST_IF
T
_SEC_PIP
E
SRST_O
SYS
S
R
ST
_F
AC
EL
LF
IF
O
S
SRS
T
_G
PT
IME
R
SRST
_T
C
SRS
T
_G
PIO
SRST
_GP
D
E
V
_C
BUS
SRS
T
_IFMT_C
B
US
S
R
ST_ISE
L_C
B
US
SRS
T
_ISY
S_C
B
US
Bit
Range
Default &
Access
Description
31:29
0h
RW
unused_reg_gp_srst:
Unused
28
0h
RW
SRST_WBUS:
soft reset bit for the wide bus