Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
1149
15.8.40
reg_gpd_irq_ctrl_reg_irq_edge_type
(gpd_irq_ctrl_reg_irq_edge)—Offset 500h
Access Method
Default: 00000000h
15.8.41
reg_gpd_irq_ctrl_reg_irq_mask_type
(gpd_irq_ctrl_reg_irq_mask)—Offset 504h
Access Method
Default: 00000000h
15.8.42
reg_gpd_irq_ctrl_reg_irq_status_type
(gpd_irq_ctrl_reg_irq_status)—Offset 508h
Indicates for each bit whether a non-masked interrupt has been generated (value='1').
Can be cleared by writing a '1' into the the corresponding bit of the req_irq_clear
register.
Type:
Memory Mapped I/O Register
(Size: 32 bits)
gpd_irq_ctrl_reg_irq_edge:
ISPMMADR Type:
PCI Configuration Register (Size: 32 bits)
ISPMMADR Reference:
[B:0, D:3, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
re
g_ir
q_ed
ge
Bit
Range
Default &
Access
Description
31:0
0h
RW
reg_irq_edge:
indicates for each bit whether an interrupt request should be generated
on a falling edge (value='0') or a rising edge (value='1').
Type:
Memory Mapped I/O Register
(Size: 32 bits)
gpd_irq_ctrl_reg_irq_mask:
ISPMMADR Type:
PCI Configuration Register (Size: 32 bits)
ISPMMADR Reference:
[B:0, D:3, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
re
g_
ir
q
_
m
as
k
Bit
Range
Default &
Access
Description
31:0
0h
RW
reg_irq_mask:
indicates for each bit of irq_di whether it can generate an interrupt
request (value='1') or not (value='0'). Setting will affect reg_irq_value as well as IRQ
output pin