Intel E3815 FH8065301567411 Data Sheet

Intel

®

 Atom™ Processor E3800 Product Family

1886

Datasheet

16

1b

RO

This bit indicates whether a card has been inserted. The 

Host Controller shall debounce this signal so that the Host Driver will not need to wait 

for it to stabilize. Changing from 0 to 1 generates a Card Insertion interrupt in the 

Normal Interrupt Status register and changing from 1 to 0 generates a Card Removal 

interrupt in the Normal Interrupt Status register. The Software Reset For All in the 

Software Reset register shall not affect this bit. If a card is removed while its power is on 

and its clock is oscillating, the Host Controller shall clear SD Bus Power in the Power 

Control register (Refer to Section 2.2.11) and SD Clock Enable in the Clock Control 

register (Refer to Section 2.2.14). When this bit is changed from 1 to 0, the Host 

Controller shall immediately stop driving CMD and DAT[3:0] (tri-state). In addition, the 

Host Driver should clear the Host Controller by the Software Reset For All in Software 

Reset register. The card detect is active regardless of the SD Bus Power. 
•

1  =  Card  Inserted 

•

0 = Reset or Debouncing or No Card 

15:12

0h

RO

Reserved.

11

0b

RO

This status is used for non-DMA read transfers. The 

Host Controller may implement multiple buffers to transfer data efficiently. This read 

only flag indicates that valid data exists in the host side buffer. If this bit is 1, readable 

data exists in the buffer. A change of this bit from 1 to 0 occurs when all the block data 

is read from the buffer. A change of this bit from 0 to 1 occurs when block data is ready 

in the buffer and generates the Buffer Read Ready interrupt. 
•

1 = Read enable 

•

0 = Read disable 

10

0b

RO

This status is used for non-DMA write transfers. 

The Host Controller can implement multiple buffers to transfer data efficiently. This read 

only flag indicates if space is available for write data. If this bit is 1, data can be written 

to the buffer. A change of this bit from 1 to 0 occurs when all the block data is written to 

the buffer. A change of this bit from 0 to 1 occurs when top of block data can be written 

to the buffer and generates the Buffer Write Ready interrupt. The Host Controller should 

neither set Buffer Write Enable nor generate Buffer Write Ready Interrupt after the last 

block data is written to the Buffer Data Port Register. 
•

1 = Write enable 

•

0 = Write disable 

9

0b

RO

This status is used for detecting completion of 

a read transfer. Refer to Section 3.12.3 for sequence details. This bit is set to 1 for either 

of the following conditions: 
•

After the end bit of the read command. 

•

When read operation is restarted by writing a 1 to Continue Request in the Block 

Gap Control register. 

This bit is cleared to 0 for either of the following conditions: 
•

When the last data block as specified by block length is transferred to the System. 

•

In case of ADMA2, end of read operation is designated by Descriptor Table. 

•

When all valid data blocks in the Host Controller have been transferred to the 

System and no current block transfers are being sent as a result of the Stop At 

Block Gap Request being set to 1. 

A Transfer Complete interrupt is generated when this bit changes to 0. 
•

1 = Transferring data 

•

0 = No valid data