Intel E3815 FH8065301567411 Data Sheet

Intel

®

 Atom™ Processor E3800 Product Family

1912

Datasheet

When ADMA Error Interrupt occurs, the ADMA Error States field in this register holds 

the ADMA state and the ADMA System Address Register holds the address around the 

error descriptor. To recover from the error, the Host Driver requires the ADMA state to 

identify the error descriptor address as follows:

• ST_STOP: Previous location set in the ADMA System Address register is the error 

descriptor address 

• ST_FDS: Current location set in the ADMA System Address register is the error 

descriptor address 

• ST_CADR: This sate is never set because do not generate ADMA error in this state. 

13

0b

RW

Reserved.

12

0b

RW

Reserved.

11:10

0h

RO

Reserved.

9

0b

RW

Force Event for ADMA Error (adma_err): 
•

1 = Interrupt is generated 

•

0 = No Interrupt 

8

0b

RW

Force Event for Auto CMD12 Error (cmd12_err): 
•

1 = Interrupt is generated 

•

0 = No Interrupt 

7

0b

RW

Force Event for Current Limit Error (cur_limit_err): 
•

1 = Interrupt is generated 

•

0 = No Interrupt 

6

0b

RW

Force Event for Data End Bit Error (data_end_bit_err): 
•

1 = Interrupt is generated 

•

0 = No Interrupt 

5

0b

RW

Event for Data CRC Error (data_crc_err): 
•

1 = Interrupt is generated 

•

0 = No Interrupt 

4

0b

RW

Event for Data Timeout Error (data_timeout_err): 
•

1 = Interrupt is generated 

•

0 = No Interrupt 

3

0b

RW

Force Event for Command Index Error (cmd_ind_err): 
•

1 = Interrupt is generated 

•

0 = No Interrupt 

2

0b

RW

Force Event for Command End Bit Error (cmd_end_bit_err): 
•

1 = Interrupt is generated 

•

0 = No Interrupt 

1

0b

RW

Force Event for Command CRC Error (cmd_crc_err): 
•

1 = Interrupt is generated 

•

0 = No Interrupt 

0

0b

RW

Force Event for Command Timeout Error (cmd_timeout_err): 
•

1 = Interrupt is generated 

•

0 No Interrupt