Intel E3815 FH8065301567411 Data Sheet

Product codes
FH8065301567411
Page of 5308
 
Intel
®
 Atom™ Processor E3800 Product Family
Datasheet
1929
17.5.7
Cache Line Size (CLS)—Offset Ch
Access Method
Default: 00h
17.5.8
Master Latency Timer (MLT)—Offset Dh
Access Method
Default: 00h
17.5.9
Header Type (HTYPE)—Offset Eh
Access Method
Default: 00h
Bit 
Range
Default & 
Access
Description
15:8
01h
RO
Base Class Code (BCC): 
Indicates that this is a mass storage device.
7:0
06h
RO
Sub Class Code (SCC): 
The value reported in this field is dependent on MAP.SMS and 
various fuses and configuration bits. The value is product specific. For VLV this field may 
read 01h (IDE) or 06h (AHCI).
Type: 
PCI Configuration Register
(Size: 8 bits)
CLS: 
7
4
0
0
0
0
0
0
0
0
0
CL
S
Bit 
Range
Default & 
Access
Description
7:0
00h
RO
Cache Line Size (CLS): 
This register has no meaning for the SATA controller.
Type: 
PCI Configuration Register
(Size: 8 bits)
MLT: 
7
4
0
0
0
0
0
0
0
0
0
ML
T
Bit 
Range
Default & 
Access
Description
7:0
00h
RO
Master Latency Timer (MLT): 
This register has no meaning for the SATA controller.
Type: 
PCI Configuration Register
(Size: 8 bits)
HTYPE: