Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
1986
Datasheet
Bit
Range
Default &
Access
Description
31
0h
RO
Cold Presence Detect Status (CPDS):
The SATA controller does not support cold
presence detect.
30
0h
RW/1C
Task File Error Status (TFES):
This bit is set whenever the status register is updated
by the device and the error bit (bit 0 of the Status field in the received FIS) is set.
29
0h
RW/1C
Host Bus Fatal Error Status (HBFS):
Indicates that the HBA encountered a host bus
error that it cannot recover from, such as a bad software pointer. In PCI, such an
indication would be a target or master abort.
28
0h
RW/1C
Host Bus Data Error Status (HBDS):
Indicates that the HBA encountered a data error
(uncorrectable ECC / parity) when reading from or writing to system memory.
27
0h
RW/1C
Interface Fatal Error Status (IFS):
Indicates that the HBA encountered an error on
the SATA interface which caused the transfer to stop.
26
0h
RW/1C
Interface Non-fatal Error Status (INFS):
Indicates that the HBA encountered an
error on the SATA interface but was able to continue operation.
25
0b
RO
RSVD0:
Reserved
24
0h
RW/1C
Overflow Status (OFS):
Indicates that the HBA received more bytes from a device
than was specified in the PRD table for the command.
23
0h
RW/1C
Incorrect Port Multiplier Status (IPMS):
Not supported
22
0h
RO
PhyRdy Change Status (PRCS):
When set to one indicates the internal PhyRdy signal
changed state. This bit reflects the state of PxSERR.DIAG.N. This bit is RO and is only
cleared when PxSERR.DIAG.N is cleared.
21:8
0b
RO
RSVD1:
Reserved
7
0h
RW/1C
Device Mechanical Presence Status (DMPS):
When set, indicates that a platform
mechanical presence switch has been opened or closed, which may lead to a change in
the connection state of the device. This bit is only valid in systems that support
mechanical presence switch (CAP.SMPS and PxCMD.MPSP are set).
6
0h
RO
Port Connect Change Status (PCS):
1=Change in Current Connect Status. 0=No
change in Current Connect Status. This bit reflects the state of PxSERR.DIAG.X. This bit
is only cleared when PxSERR.DIAG.X is cleared.
5
0h
RW/1C
Descriptor Processed (DPS):
A PRD with the I. bit set has transferred all of its data.
4
0h
RO
Unknown FIS Interrupt (UFS):
When set to 1 indicates that an unknown FIS was
received and has been copied into system memory. This bit is cleared to 0 by software
clearing the PxSERR.DIAG.F bit to 0. Note that this bit does not directly reflect the
PxSERR.DIAG.F bit. PxSERR.DIAG.F is set immediately when an unknown FIS is
detected, whereas this bit is set when the FIS is posted to memory. Software should
wait to act on an unknown FIS until this bit is set to 1 or the two bits may become out of
sync.
3
0h
RW/1C
Set Device Bits Interrupt (SDBS):
A Set Device Bits FIS has been received with the
I. bit set and has been copied into system memory.
2
0h
RW/1C
DMA Setup FIS Interrupt (DSS):
A DMA Setup FIS has been received with the I. bit
set and has been copied into system memory.
1
0h
RW/1C
PIO Setup FIS Interrupt (PSS):
A PIO Setup FIS has been received with the I. bit
set, it has been copied into system memory, and the data related to that FIS has been
transferred. This bit shall be set even if the data transfer resulted in an error.
0
0h
RW/1C
Device to Host Register FIS Interrupt (DHRS):
A D2H register FIS has been
received with the I. bit set, and has been copied into system memory.