Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
1987
17.8.32
Port-Interrupt Enable (PxIE1)—Offset 194h
Access Method
Default: 00000000h
Type:
Memory Mapped I/O Register
(Size: 32 bits)
PxIE1:
ABAR Type:
PCI Configuration Register (Size: 32 bits)
ABAR Reference:
[B:0, D:19, F:0] + 24h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CP
DS
TFE
E
HBF
E
HBD
E
IF
E
IN
FE
RSV
D
0
OF
E
IPME
PRCE
RSV
D
1
DMPE
PCE
DPE
UF
E
SDB
E
DS
E
PSE
DHR
E
Bit
Range
Default &
Access
Description
31
0h
RO
Cold Presence Detect Enable (CPDS):
The SATA controller does not support cold
presence detect.
30
0h
RW
Task File Error Enable (TFEE):
When set, GHC.IE is set, and P0S.TFES is set, the HBA
shall generate an interrupt.
29
0h
RW
Host Bus Fatal Error Enable (HBFE):
When set, GHC.IE is set, and P0IS.HBFS is set,
the HBA shall generate an interrupt.
28
0h
RW
Host Bus Data Error Enable (HBDE):
When set, GHC.IE is set, and P0IS.HBDS is set,
the HBA shall generate an interrupt.
27
0h
RW
Interface Fatal Error Enable (IFE):
When set, GHC.IE is set, and P0IS.IFS is set, the
HBA shall generate an interrupt.
26
0h
RW
Interface Non-fatal Error Enable (INFE):
When set, GHC.IE is set, and P0IS.INFS is
set, the HBA shall generate an interrupt.
25
0b
RO
RSVD0:
Reserved
24
0h
RW
Overflow Enable (OFE):
When set, and GHC.IE and P0IS.OFS are set, the HBA shall
generate an interrupt.
23
0h
RW
Incorrect Port Multiplier Enable (IPME):
When set, and GHC.IE and P0IS.IPMS are
set, the HBA shall generate an interrupt.
22
0h
RW
PhyRdy Change Interrupt Enable (PRCE):
When set, and GHC.IE is set, and
PxIS.PRCS is set, the HBA shall generate an interrupt.
21:8
0b
RO
RSVD1:
Reserved
7
0h
RW
Device Mechanical Enable (DMPE):
When set, and P0IS.DMPS is set, the HBA shall
generate an interrupt.
6
0h
RW
Port Change Interrupt Enable (PCE):
When set, GHC.IE is set, and P0IS.PCS is set,
the HBA shall generate an interrupt.
5
0h
RW
Descriptor Processed Interrupt Enable (DPE):
When set, GHC.IE is set, and
P0IS.DPS is set, the HBA shall generate an interrupt.
4
0h
RW
Unknown FIS Interrupt Enable (UFE):
When set, GHC.IE is set, and PxIS.UFS is set
to 1, the HBA shall generate an interrupt.
3
0h
RW
Set Device Bits FIS Interrupt Enable (SDBE):
When set, GHC.IE is set, and
P0IS.SDBS is set, the HBA shall generate an interrupt.