Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
2025
17.17.7
PCS_DWORD6 (pcs_dword6)—Offset 18h
Access Method
Default: FFFFFFFFh
22
0h
RW
cri_dfx_marginmode:
Margin mode Overrides standard setup configurations for use
with Eye Width Margining. 0 : Standard Mode (default) 1 : Margin Mode enabled
21
0h
RW
cri_dfx_chk_sel:
Pattern Checker 8b10b Select This determines where Rx data is
compared, either in the 10-bit domain before decode or after 10b-)8b decoding. 0: 10b
domain 1: 8b domain
20
0h
RW
cri_dfx_patchken:
Pattern Checker Enable 0 : Disable Pattern Checker (default) 1 :
Enable Pattern Checker
19
0h
RW
cri_dfx_patgenen:
Pattern Generator Enable This will activate the DFx bypass muxes
in the PCS Tx path. 0 : Disable Pattern Generator (default) 1 : Enable Pattern Generator
18
0h
RW
cri_dfx_clrerrcnt:
Clear Error Counter Resets the Pattern Checker's error counter. 0 :
Error Counter allowed to run (default) 1 : Error Counter held in reset
17
0h
RW
cri_dfx_lcereset:
Local Compare Engine Reset Resets all components of the Local
Compare Engine in both the Pattern Generator and the Pattern Checker. 0 : LCE not in
reset (default) 1 : LCE in reset
16
0h
RW
cri_dfx_lcestart:
Local Compare Engine Start Controls the starting and stopping of
the LCE. Allows for simultaneous or independent start across lanes. Once stopped, a
DFXLCERESET is usually required. 0 : LCE stopped (default) 1 : LCE running
15:8
3Eh
RW
cri_dfx_patbuf_7_0:
Pattern Buffer Storage In 10b mode, the buffer is read as eight
10b chunks. The first 10 bits should not equal the Comma Symbol: '0011111010' (or its
inversion '1100000101'). In 8b mode, the buffer is read as eight 10b chunks, where the
10th bit is unused and the 9th bit is the K-bit indicator. The first 10 bits should not
equal the Comma Symbol: 'xx10111100'. DFXPATBUF[78] should not = '1'.
7:0
63h
RW
cri_dfx_patbuf_15_8:
Pattern Buffer Storage See cri_dfx_patbuf[7:0] description.
Bit
Range
Default &
Access
Description
Type:
Message Bus Register
(Size: 32 bits)
pcs_dword6:
Op Codes:
0h - Read, 1h - Write
0h - Read, 1h - Write
31
28
24
20
16
12
8
4
0
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
cri_dfx_prbsseed_7_0
cri_dfx_pr
bss
eed_15_8
cri
_
dfx_pr
bss
eed_23_16
cri
_
dfx_pr
bss
eed_31_24
Bit
Range
Default &
Access
Description
31:24
FFh
RW
cri_dfx_prbsseed_7_0:
PRBS Seed Can be used for HVM determinism. The use of all
zeroes can result in lockup.