Intel E3815 FH8065301567411 Data Sheet

Intel

®

 Atom™ Processor E3800 Product Family

2028

Datasheet

Default: 00000000h

26:24

0h

RW

Override for cdr_override strap

23

0h

RW

Override for ebuffmode (no functionality in p1271 phase1 design)

22:21

0h

RW

Selects the active clock channel

20

0h

RW

When asserted selects reg_usedclockchannel[1:0]

19

0h

RW

Global override select

18

0h

RW

When asserted keeps PCLK running in P2 mode. For DP this is 

used for Lane1

17

0h

RW

When asserted keeps PCLK running in P2 mode. This is 

reserved (no impact) for PCIe/DMI and used for DP Lane2

16

0h

RW

Override for i_txenable for tx2

15:12

0h

RW

Config override for initial value of Rx elastic buffer read 

pointer

11

0h

RW

When asserted overrides for Tx power fsm are selected

10

0h

RW

Override for suspend

9

0h

RW

Override for pclkcfginput strap

8

0h

RW

Override for useqclock; MUX select for I or Q clk for TX clocking

7:4

Ch

RW

Elastic buffer high watermark based on which SKP is 

removed

3:0

4h

RW

Elastic buffer low watermark based on which SKP is added

Message Bus Register

(Size: 32 bits)

Op Codes:
0h - Read, 1h - Write