Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
2035
Default: 007A0018h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0
re
g_clkbu
f_stagge
r_o
vrd
reg_clkbuf_stagger_cn
t_10
re
g
_
sl
ow
clk
_
ov
rd
en
reg_tx
loadge
n
en2tx
en
_fall_dela
y_4_0
o_cmlmuxst
hsel_3_0
o_cmlst
h
sel_3_0
o_pc
isel_3_0
o_
pcqsel_3_0
o_
p
h
as
ei
ce
n
o_p
h
ase
q
ce
n
o_pc
byp
ass
o_slo
w
cl
ock
en
o_sc
lk250e
n
cr
i_kalign
_com_cnt
Bit
Range
Default &
Access
Description
31
0h
RW
reg_clkbuf_stagger_ovrd:
Override enable for reg_clkbuf_stagger_cnt
30
0h
RW
reg_clkbuf_stagger_cnt_10:
Counter override value for staggering delay of clock
buffer control signals.
29
0h
RW
reg_slowclk_ovrden:
Slow Clock Override Enable When set 1'b1, reg_slowclocken
and reg_sclk250en are valid. When cleared 1'b0, output of FSM will drive slow clock
enable.
28:24
0h
RW
reg_txloadgenen2txen_fall_delay_4_0:
reserved
23:20
7h
RW
o_cmlmuxsthsel_3_0:
CML Mux strength control
19:16
Ah
RW
o_cmlsthsel_3_0:
RX CML driver strength
15:12
0h
RW
o_pcisel_3_0:
I clk phase correction control
11:8
0h
RW
o_pcqsel_3_0:
Q clk phase correction control
7
0h
RW
o_phaseicen:
Iclk phase correction enable.
6
0h
RW
o_phaseqcen:
Qclk phase correction enabled.
5
0h
RW
o_pcbypass:
Phase correction bypass.
4
1h
RW
o_slowclocken:
Slow clock 1 enable Only valid if slow clock override enable is set 1'b1
3
1h
RW
o_sclk250en:
Slow clock 2 enable Only valid if slow clock override enable is set 1'b1
2:0
0h
RW
cri_kalign_com_cnt:
Upper 3 bits of a 7-bit counter that counts number of COM
characters found. Used for special SAPIS mode where spread spectrum clocking can be
utilized. Note: This register is used in conjunction with another PCS register
cri_kalignmode[1:0] = 10 Register value Minimum COM count to achieve symbol lock
000 - 18 001 - 34 010 - 50 011 - 66 100 - 82 101 - 98 110 - 114 111 - 130