Intel E3815 FH8065301567411 Data Sheet

Intel

®

 Atom™ Processor E3800 Product Family

2072

Datasheet

31

0h

RW

Pattern Buffer Manual Training When DFXPATBUFTRAINOVR and 

DFXLCESTART are asserted, this manually controls whether the Pattern Buffers are in 

training or have completed training. 0 : Send training patterns (default) 1 : Send 

contents of DFXPATBUF

30:28

0h

RW

PRBS Polynomial Select the polynomial to be used by the 

PRBS in the Pattern Generator and Pattern Checker. PRBS support 10b or 8b, which is 

indicated by the msb. 000 - x^16 + x^5 + x^4 + x^3 + 1 (USB3/PCIe Scrambler) (8b) 

001 - x^16 + x^15 + x^13 + x^4 + 1 (SATA scrambler) (8b) 010 - x^31 + x^28 + 1 

(8b) 011 - x^7 + x^6 + 1 (8b) 100 - x^15 + x^14 + 1 (10b) 101 - x^23 + x^18 + 1 

(10b) 110 - x^31 + x^28 + 1 (10b) 111 - x^7 + x^6 + 1 (10b)

27:26

0h

RW

Pattern Buffer Size Select the size of the Pattern Buffer to 

use. The MSB will always be bit 79. The LSB will depend on this select and the 

DFXLCEDATAWIDTH (10b or 8b mode). 00 : full 80b buffer (Default) 01 : 70b (while in 

10b mode), 56b (while in 8b mode) 10 : 40b (while in 10b mode), 32b (while in 8b 

mode) 11 : 10b (while in 10b mode), 8b (while in 8b mode)

25

0h

RW

Pattern Buffer Looping Enable Enables looping of the Patter 

Buffer. By default, the contents of Pattern Buffer will be used once and stop. 

Alternatively, the Pattern Buffer will continue to loop until the DFXLCESTART is de-

asserted. 0 : Run Pattern Buffer only once (default) 1 : Loop Pattern Buffer until 

stopped

24

0h

RW

Pattern Buffer Data Width Selects between 10 bit or 8 bit data 

width for the Pattern Buffer. Determines where in the Tx/Rx path the data is inserted/

retrieved. 0 : 10b (default) 1 : 8b

23

0h

RW

Pattern Buffer Training Override Enables manual training of 

the Pattern Buffer instead of the automated coordination between the Pattern Checker 

and Patter Generator. When asserted, the DFXPATBUFTRAIN bit will be used to force 

when training is active and when it is complete. 0 : Automatic Training (default) 1 : 

Enable Manual Training

22

0h

RW

Margin mode Overrides standard setup configurations for use 

with Eye Width Margining. 0 : Standard Mode (default) 1 : Margin Mode enabled

21

0h

RW

Pattern Checker 8b10b Select This determines where Rx data is 

compared, either in the 10-bit domain before decode or after 10b-)8b decoding. 0: 10b 

domain 1: 8b domain

20

0h

RW

Pattern Checker Enable 0 : Disable Pattern Checker (default) 1 : 

Enable Pattern Checker

19

0h

RW

Pattern Generator Enable This will activate the DFx bypass muxes 

in the PCS Tx path. 0 : Disable Pattern Generator (default) 1 : Enable Pattern Generator

18

0h

RW

Clear Error Counter Resets the Pattern Checker's error counter. 0 : 

Error Counter allowed to run (default) 1 : Error Counter held in reset

17

0h

RW

Local Compare Engine Reset Resets all components of the Local 

Compare Engine in both the Pattern Generator and the Pattern Checker. 0 : LCE not in 

reset (default) 1 : LCE in reset

16

0h

RW

Local Compare Engine Start Controls the starting and stopping of 

the LCE. Allows for simultaneous or independent start across lanes. Once stopped, a 

DFXLCERESET is usually required. 0 : LCE stopped (default) 1 : LCE running

15:8

3Eh

RW

Pattern Buffer Storage In 10b mode, the buffer is read as eight 

10b chunks. The first 10 bits should not equal the Comma Symbol: '0011111010' (or its 

inversion '1100000101'). In 8b mode, the buffer is read as eight 10b chunks, where the 

10th bit is unused and the 9th bit is the K-bit indicator. The first 10 bits should not 

equal the Comma Symbol: 'xx10111100'. DFXPATBUF[78] should not = '1'.

7:0

63h

RW

Pattern Buffer Storage See cri_dfx_patbuf[7:0] description.