Intel E3815 FH8065301567411 Data Sheet

Intel

®

 Atom™ Processor E3800 Product Family

2074

Datasheet

Default: 000000C4h

31:24

X

RO

Error Counter Tracks how many bit errors the Pattern Checker 

has detected. Can be cleared using DFXCLRERRCNT or DFXLCERESET.

23:16

X

RO

Error Counter Tracks how many bit errors the Pattern Checker 

has detected. Can be cleared using DFXCLRERRCNT or DFXLCERESET.

15

X

RO

RX Calibration Cycles Complete Indicator

14

X

RO

Local Compare Engine Margin Error Indicates that the error 

counter has reached its max value. This can be used by the Rx upartition during Margin 

Mode to determine when the eye width has closed.

13

X

RO

Pattern Generator 2 Active status indicator In a lane with two 

Tx paths, this indicates that the second Pattern Generator is in progress. The 

DFXPATGENACTIVE will only indicate that the first Pattern Generator is in progress.

12

X

RO

Pattern Buffer All Fail status indicator Indicates that there has 

not been a single matching Pattern Buffer pattern. This could signify that an error 

occured during training.

11

X

RO

Pattern Checker Active status indicator Indicates that the 

Pattern Checker is in progress (either Pattern Buffer or PRBS).

10

X

RO

Pattern Generator Active status indicator Indicates that the 

Pattern Generator is in progress (either Pattern Buffer or PRBS).

9

X

RO

Local Compare Engine Training Done status indicator Indicates 

that the Pattern Checker training is completed (either Pattern Buffer or PRBS). The 

Pattern Checker is now synchronized to the Pattern Generator.

8

X

RO

Local Compare Engine Training Active status indicator 

Indicates that the Pattern Checker training is in progress (either Pattern Buffer or 

PRBS).

7

0h

RW

reserved

6

0h

RW

Pattern Generator 2 Enable In a lane with two Tx paths, this 

enables the second Pattern Generator. The DFXPATGENEN will enable the first Pattern 

Generator. 0 : Disable second Pattern Generator (default) 1 : Enable second Pattern 

Generator

5:4

0h

RW

Maximum Error Count Selectable maximum value that the 

DFXERRCNT can reach before the Local Compare Engine is automatically stopped. 00 : 

2^16 (default) 01 : 2^10 10 : 2^8 11 : 2^4

3:0

9h

RW

PRBS Training Count The number of consecutive cycles 

that the Pattern Checker's PRBS must be error free before it is considered 

synchronized. Default is 9.

Message Bus Register

(Size: 32 bits)

Op Codes:
0h - Read, 1h - Write