Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
2202
Datasheet
18.7.30
Port 8 Status and Control USB2 (PORTSC5USB2)—Offset 4C0h
Access Method
Default: 000002A0h
13:10
0h
RW
Host Initiated Resume Duration-Deep (HIRDD):
System software sets this field to
indicate to the recipient device how long the xHC will drive resume upon exit from L1.
The HIRDD value is is encoded as follows:
•
•
0h = 50 us (default)
•
1h = 125 us
•
2h = 200 us
•
...
•
Fh = 1.175ms
The value of 0h is interpreted as 50 us. Each incrementing value adds 75 us to the
previous value.
Power Well:
SUS
9:2
00h
RW
L1 Timeout (L1TO):
Timeout value for L1 inactivity timer. This field shall be set to 00h
by assertion of PR to '1'. Following are permissible values: 00h: 128 us (default) 01h:
256 us. ... FFh: 65,280us Note: This register is sticky.
Power Well:
SUS
1:0
0h
RW
Host Initiated Resume Duration Mode (HIRDM):
Indicates which HIRD value
should be used. The following are permissible values:
•
•
0 = Initiate L1 using HIRD only time out (default)
•
1 = Initiate HIRDDon timeout. If rejected by device, initiate L1 using HIRD
•
2,3 = Reserved
Note: This register is sticky.
Power Well:
SUS
Bit
Range
Default &
Access
Field Name (ID): Description
Type:
Memory Mapped I/O Register
(Size: 32 bits)
Offset:
MBAR Type:
PCI Configuration Register (Size: 64 bits)
MBAR Reference:
[B:0, D:20, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 0 0 0
WP
R
DR
Rsvd2
WOE
WDE
WC
E
CAS
CE
C
PL
C
PRC
OC
C
WRC
PE
C
CS
C
LW
S
PIC
Po
rt
_
S
p
ee
d
PP
PLS
PR
OC
A
Rsvd1
PE
D
CC
S
Bit
Range
Default &
Access
Field Name (ID): Description
31
0b
RW/S
Warm Port Reset (WPR):
Reserved.
Power Well:
SUS
30
0b
RO
Device Removable (DR):
Reserved.
Power Well:
Core