Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
2226
Datasheet
18.7.60
Event Ring Dequeue Pointer High 3 (ERDP_HI3)—Offset 207Ch
There are 8 ERDP_HIx registers, with x = 1, 2, ... 8.
Access Method
Default: 00000000h
18.7.61
Interrupter 4 Management (IMAN4)—Offset 2080h
The Interrupter Management registers allow system software to enable, disable, detect
and force xHC interrupts. There are 8 IMAN registers. x = 1, 2, ... 8.
Access Method
Default: 00000000h
2:0
0h
RW
Dequeue ERST Segment Index (DESI):
This field may be used by the xHC to
accelerate checking the Event Ring full condition. This field is written with the low order
3 bits of the offset of the ERST entry which defines the Event Ring segment that the
Event Ring Dequeue Pointer resides in.
Power Well:
Core
Bit
Range
Default &
Access
Field Name (ID): Description
Type:
Memory Mapped I/O Register
(Size: 32 bits)
Offset:
MBAR Type:
PCI Configuration Register (Size: 64 bits)
MBAR Reference:
[B:0, D:20, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ERD
P
Bit
Range
Default &
Access
Field Name (ID): Description
31:0
00000000h
RW
Event Ring Dequeue Pointer (ERDP):
This field defines the high order bits of the 64-
bit address of the current Event Ring Dequeue Pointer.
Power Well:
Core
Type:
Memory Mapped I/O Register
(Size: 32 bits)
Offset:
MBAR Type:
PCI Configuration Register (Size: 64 bits)
MBAR Reference:
[B:0, D:20, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Rsvd
1
IE
IP