Intel E3815 FH8065301567411 Data Sheet

Product codes
FH8065301567411
Page of 5308
Intel
®
 Atom™ Processor E3800 Product Family
2248
Datasheet
Default: 00000000h
18.7.96
Door Bell 1 (DOORBELL1)—Offset 3000h
Door Bell registers are an array of 64 registers, with 0 to 32 being used by the XHC and 
the rest being reserved. Refer to the xHCI for USB specification for more information.
Access Method
Default: 00000000h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ER
DP
Bit 
Range
Default & 
Access
Field Name (ID): Description
31:0
00000000h
RW
Event Ring Dequeue Pointer (ERDP): 
This field defines the high order bits of the 64- 
bit address of the current Event Ring Dequeue Pointer.
Power Well: 
Core
Type: 
Memory Mapped I/O Register
(Size: 32 bits)
Offset: 
MBAR Type: 
PCI Configuration Register (Size: 64 bits)
MBAR Reference: 
[B:0, D:20, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DBS
ID
Rsvd
1
DB
T
Bit 
Range
Default & 
Access
Field Name (ID): Description
31:16
0000h
RW
DB Stream ID (DBSID): 
If the endpoint of a Device Context Doorbell defines Streams, 
then this field shall be used to identify which Stream of the endpoint the doorbell 
reference is targeting. System software is responsible for ensuring that the value 
written to this field is valid.  
If the endpoint defines Streams (MaxPStreams ) 0), then 0, 65535 (No Stream) and 
65534 (Prime) are reserved Stream ID values and shall not be written to this field. If the 
endpoint does not define Streams (MaxPStreams = 0) and a non-'0' value is written to 
this field, the doorbell reference shall be ignored.  
This field only applies to Device Context Doorbells and shall be cleared to 0 for Host 
Controller Command Doorbells
.[br 
 
This field returns 0 when read.
Power Well: 
Core
15:8
00h
RO
Rsvd1: 
Reserved.
Power Well: 
Core