Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
2383
18.9.11 Configure Flag Register (CONFIGFLAG)—Offset 60h
Access Method
Default: 00000000h
Type:
Memory Mapped I/O Register
(Size: 32 bits)
Offset:
MBAR Type:
PCI Configuration Register (Size: 32 bits)
MBAR Reference:
[B:0, D:29, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RSVD
CF_0
Bit
Range
Default
& Access
Field Name (ID): Description
31:1
00000000h
RO
Reserved (RSVD): Reserved.
0
0b
RW
Configure Flag (CF_0): Host software sets this bit as the last action in its
process of configuring the Host Controller. This bit controls the default port-
routing control logic. Bit values and side-effects are listed below. See section
4 of the EHCI spec for operation details. 0b Port routing control logic default-
routes each port to the classic host controllers. 1b Port routing control logic
default-routes all ports to this host controller. This register is in the suspend
power well. It is only reset by hardware when the suspend power is initially
applied or in response to a host controller reset.
process of configuring the Host Controller. This bit controls the default port-
routing control logic. Bit values and side-effects are listed below. See section
4 of the EHCI spec for operation details. 0b Port routing control logic default-
routes each port to the classic host controllers. 1b Port routing control logic
default-routes all ports to this host controller. This register is in the suspend
power well. It is only reset by hardware when the suspend power is initially
applied or in response to a host controller reset.
Power Well: Resume