Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
2403
19:16
0h
RW
Port Test Control (PTC_P0_0): When this field is zero, the port is NOT
operating in a test mode. A non-zero value indicates that it is operating in
test mode and the specific test mode is indicated by the specific value. The
encoding of the test mode bits are (0110b - 1111b are reserved): Bits Test
Mode 0000b Test mode not enabled 0001b Test J_STATE- During this test
mode the hardware forces pre-emphasis disabled to the AFE if bit 29 of the
USB2 Safe Mode Register is set (config offset FCh.bit 29) 0010b Test
K_STATE- During this test mode the hardware forces pre-emphasis disabled
to the AFE if bit 29 of the USB2 Safe Mode Register is set (config offset
FCh.bit 29) 0011b Test SE0_NAK 0100b Test Packet 0101b Test
FORCE_ENABLE Refer to USB Specification Revision 2.0, Chapter 7 and the
EHCI specification, Chapter 4 for details on each test mode. The EHC does
not support the option to run the port tests while the Run/Stop bit is a one.
operating in a test mode. A non-zero value indicates that it is operating in
test mode and the specific test mode is indicated by the specific value. The
encoding of the test mode bits are (0110b - 1111b are reserved): Bits Test
Mode 0000b Test mode not enabled 0001b Test J_STATE- During this test
mode the hardware forces pre-emphasis disabled to the AFE if bit 29 of the
USB2 Safe Mode Register is set (config offset FCh.bit 29) 0010b Test
K_STATE- During this test mode the hardware forces pre-emphasis disabled
to the AFE if bit 29 of the USB2 Safe Mode Register is set (config offset
FCh.bit 29) 0011b Test SE0_NAK 0100b Test Packet 0101b Test
FORCE_ENABLE Refer to USB Specification Revision 2.0, Chapter 7 and the
EHCI specification, Chapter 4 for details on each test mode. The EHC does
not support the option to run the port tests while the Run/Stop bit is a one.
Power Well: Resume
15:14
00b
RW
Port Indicator Control (PIC_P0_0): Writing to these bits directly controls
the corresponding LED output pins. Bit 15 is inverted to generate
USBLEDG#(n) where n is the port number. Bit 14 is inverted to generate
USBLEDA#(n). Software is responsible for controlling these as specified in
the USB Specification Revision 2.0. Bit Value Meaning 00b Port indicators are
off 01b Amber 10b Green 11b Undefined The Intel EHC only supports bit
value of 00b. Other values will result in unspecified behavior.
the corresponding LED output pins. Bit 15 is inverted to generate
USBLEDG#(n) where n is the port number. Bit 14 is inverted to generate
USBLEDA#(n). Software is responsible for controlling these as specified in
the USB Specification Revision 2.0. Bit Value Meaning 00b Port indicators are
off 01b Amber 10b Green 11b Undefined The Intel EHC only supports bit
value of 00b. Other values will result in unspecified behavior.
Power Well: Resume
13
1b
RW
Port Owner (PO_P0_0): This bit unconditionally goes to a 0b when the
Configure Flag makes a 0b to 1b transition. This bit unconditionally goes to
1b whenever the Configure Flag bit is zero. System software uses this field to
release ownership of the port to a selected host controller (in the event that
the attached device is not a high-speed device). Software writes a one to this
bit when the attached device is not a high-speed device. A one in this bit
means that a companion host controller owns and controls the port. See
Section 4 of the EHCI Specification for operational details.
Configure Flag makes a 0b to 1b transition. This bit unconditionally goes to
1b whenever the Configure Flag bit is zero. System software uses this field to
release ownership of the port to a selected host controller (in the event that
the attached device is not a high-speed device). Software writes a one to this
bit when the attached device is not a high-speed device. A one in this bit
means that a companion host controller owns and controls the port. See
Section 4 of the EHCI Specification for operational details.
Power Well: Resume
12
1b
RO
Port Power (PP_P0_0): Hard-wired with a value of '1' on the Intel EHC.
This indicates that the port does have power.
This indicates that the port does have power.
Power Well: Resume
11:10
00b
RO
Line Status (LS_P0_0): These bits reflect the current logical levels of the
D+ (bit 11) and D- (bit 10) signal lines. These bits are used for detection of
low-speed USB devices prior to the port reset and enable sequence. This field
is valid only when the port enable bit is zero and the current connect status
bit is set to a one. The encoding of the bits are: Bits(11:10) USB State
Interpretation 00b SE0 Not Low-speed device, perform EHCI reset 10b J-
state Not Low-speed device, perform EHCI reset 01b K-state Low-speed
device, release ownership of port 11b Undefined Not Low-speed device,
perform EHCI reset
D+ (bit 11) and D- (bit 10) signal lines. These bits are used for detection of
low-speed USB devices prior to the port reset and enable sequence. This field
is valid only when the port enable bit is zero and the current connect status
bit is set to a one. The encoding of the bits are: Bits(11:10) USB State
Interpretation 00b SE0 Not Low-speed device, perform EHCI reset 10b J-
state Not Low-speed device, perform EHCI reset 01b K-state Low-speed
device, release ownership of port 11b Undefined Not Low-speed device,
perform EHCI reset
Power Well: Resume
Bit
Range
Default
& Access
Field Name (ID): Description