Intel E3815 FH8065301567411 Data Sheet

 

Intel

®

 Atom™ Processor E3800 Product Family

Datasheet

2457

General Purpose Read Write Register2

Default: 00000000h

19

0b

RW

Determines whether ULPI flis PME events are allowed to trigger PME 

events to brige/GPIO

18

0b

RW

Determines whether core PME events are allowed to trigger PME events 

to brige/GPIO

17

0b

RW

Feeds logic that generates the 19.2MHz clkreq signal

16

0b

RW

Feeds through PIMA PHY into 25MHz clkreq signal

15:14

00b

RW

Indicates if the device attached to a downstream port is 

permanently attached or not

13

0b

RW

This port defines the bit [3] of Capability Parameters 

(HCCPARAMS). Change the PPC value through the pin Port Power Control (PPC). This 

indicates whether the host controller implementation includes port power control. ? 0 - 

Indicates that the port does not have port power switches. ? 1 - Indicates that the port 

has port power switches.

12

0b

RW

This signal is used to select the xHCI revision that the host controller 

complies with

11:8

0000b

RW

Bus Filter Bypass. Disables the internal bus filters that are enabled 

by DWC_USB3_EN_BUS_FILTERS coreConsultant parameter. This static signal is present 

only when DWC_USB3_EN_BUS_FILTERS is 1. It is expected that this signal is set or 

reset at power-on reset and is not changed during the normal operation of the core.

7

0b

RW

reserved

6

0b

RW

reserved

5

0b

RW

Indicates that PHY suspend power should not power off even 

on RTD3hot (Note that the PHY core power is turned off during RTD3hot in line with the 

OTG core, as a function of otg_cnt_pwr_off_veto)

4

0b

RW

Indicates that controller power should not power off even on 

RTD3hot.Also a veto signal to keep LPPLL on. Note: Currently LPPLL results in a veto for 

S0iX flows

3

0b

RW

reset the core see also regRW1[31]

2

0b

RW

reserved

1:0

00b

RW

This port defines the PCI power management state 

requested by the software. When the core is configured with two power rail support 

(DWC_USB3_EN_PWROPT=2), the valid states are: ? 00: D0 ? 11: D3 Active State

PCI Configuration Register

(Size: 32 bits)