Intel E3815 FH8065301567411 Data Sheet

 

Intel

®

 Atom™ Processor E3800 Product Family

Datasheet

2471

Doorbell Offset Register

15:12

fh

RO

Maximum Primary Stream Array Size

11:10

0h

RO

Reserved

9

0h

RO

Secondary Bandwidth Domain Reporting (SBD)

8

0h

RO

For xHCI 0.96, this field is Force Stopped Event (FSE) / For xHCI 1.0, this field is 

Parse All Event Data (PAE)

7

0h

RO

No Secondary SID Support (NSS). This flag indicates whether the host controller 

implementation supports Secondary Stream IDs. A 1 in this bit indicates that Secondary 

Stream ID decoding is not supported. A 0 in this bit indicates that Secondary Stream ID 

decoding is supported. (refer to Sections 4.12.2 and 6.2.3).

6

1h

RO

Latency Tolerance Messaging Capability (LTC). This flag indicates whether the host 

controller implementation supports Latency Tolerance Messaging (LTM). A 1 in this bit 

indicates that LTM is supported. A 0 in this bit indicates that LTM is not supported. Refer 

to section 4.13.1 for more information on LTM.

5

0h

RO

Light HC Reset Capability (LHRC). This flag indicates whether the host controller 

implementation supports a Light Host Controller Reset. A 1 in this bit indicates that Light 

Host Controller Reset is supported. A 0 in this bit indicates that Light Host Controller 

Reset is not supported. The value of this flag affects the functionality of the Light Host 

Controller Reset (LHCRST) flag in the USBCMD register (refer to Section 5.4.1).

4

0h

RO

Port Indicators (PIND). This bit indicates whether the xHC root hub ports support 

port indicator control. When this bit is a 1, the port status and control registers include a 

read/writeable field for controlling the state of the port indicator. Refer to Section 5.4.8 

for definition of the Port Indicator Control field.

3

1h

RO

Port Power Control (PPC). This flag indicates whether the host controller 

implementation includes port power control. A 1 in this bit indicates the ports have port 

power switches. A 0 in this bit indicates the port do not have port power switches. The 

value of this flag affects the functionality of the PP flag in each port status and control 

register (refer to Section 5.4.8).

2

1h

RO

Context Size (CSZ). If this bit is set to 1, then the xHC uses 64 byte Context data 

structures. If this bit is cleared to 0, then the xHC uses 32 byte Context data structures. 

Note: This flag does not apply to Stream Contexts.

1

0h

RO

BW Negotiation Capability (BNC). This flag identifies whether the xHC has 

implemented the Bandwidth Negotiation. Values for this flag have the following 

interpretation: for Value 0 Description BW Negotiation not implemented. for Value 1 

DescriptionBW Negotiation implemented. Refer to section 4.16 of XHCI specification for 

more information on Bandwidth Negotiation.

0

0h

RO

64-bit Addressing Capability (AC64). This flag documents the addressing range 

capability of this implementation. The value of this flag determines whether the xHC has 

implemented the high order 32 bits of 64 bit register and data structure pointer fields. 

Values for this flag have the following interpretation: for Value 0 Description 32-bit 

address memory pointers implemented. for Value 1 description 64-bit address memory 

pointers implemented. If 32-bit address memory pointers are implemented, the xHC 

shall ignore the high order 32 bits of 64 bit data structure pointer fields, and system 

software shall ignore the high order 32 bits of 64 bit xHC registers.

Memory Mapped I/O Register

(Size: 32 bits)

PCI Configuration Register (Size: 32 bits)

[B:0, D:22, F:0] + 10h