Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
High Definition Audio
Intel
®
Atom™ Processor E3800 Product Family
2662
Datasheet
20
Intel
®
High Definition Audio
The Intel
®
High Definition Audio (Intel
®
HD Audio) is an architecture and infrastructure
to support high-quality audio implementations for PCs.
Note:
The High Definition Audio interface is multiplexed on the same balls as LPE_I2S[1:0].
Note:
When High Definition Audio is active, the LPE Audio functionality is disabled.
The Intel
®
High Definition Audio (Intel
®
HD Audio) controller consists of a set of DMA
engines that are used to move samples of digitally encoded data between system
memory and internal/external CODECs. The controller communicates with the internal/
external CODECs over the Intel
memory and internal/external CODECs. The controller communicates with the internal/
external CODECs over the Intel
®
HD Audio serial link.The output DMA engines move
digital data from system memory to a D-A converter in a CODEC. The SoC implements
a single Serial Data Output (SDO) signal that is connected to the external CODECs. The
input DMA engines move digital data from the A-D converter in the CODEC to system
memory. The platform supports up to two external CODECs by implementing two
a single Serial Data Output (SDO) signal that is connected to the external CODECs. The
input DMA engines move digital data from the A-D converter in the CODEC to system
memory. The platform supports up to two external CODECs by implementing two
Serial
Data Input (SDI) signals, each being dedicated to a single CODEC.
Audio software renders outbound, and processes inbound data to/from buffers in
memory. The location of the individual buffers is described by a Buffer Descriptor List
that is fetched and processed by the audio controller. The data in the buffers is
arranged in a pre-defined format. The output DMA engines fetch the digital data from
memory and reformat it based on the programmed sample rate, bits/sample and
number of channels. The data from the output DMA engines is then combined and
serially sent to the CODEC(s) over the Intel
memory. The location of the individual buffers is described by a Buffer Descriptor List
that is fetched and processed by the audio controller. The data in the buffers is
arranged in a pre-defined format. The output DMA engines fetch the digital data from
memory and reformat it based on the programmed sample rate, bits/sample and
number of channels. The data from the output DMA engines is then combined and
serially sent to the CODEC(s) over the Intel
®
HD Audio link. The input DMA engines
receive data from the CODEC(s) over the Intel
®
HD Audio link and format the data
based on the programmable attributes for that stream. The data is then written to
memory in the predefined format for software to process. Each DMA engine moves one
“stream” of data. A single CODEC can accept or generate multiple “streams” of data,
one for each A-D or D-A converter in the CODEC. Multiple CODECs can accept the same
output “stream” processed by a single DMA engine.
memory in the predefined format for software to process. Each DMA engine moves one
“stream” of data. A single CODEC can accept or generate multiple “streams” of data,
one for each A-D or D-A converter in the CODEC. Multiple CODECs can accept the same
output “stream” processed by a single DMA engine.
HD Audio
IO