Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
High Definition Audio
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
2663
Codec commands and responses are also transported to and from the CODEC via DMA
engines. The DMA engine dedicated to transporting commands from the Command
Output Ring Buffer (CORB) in memory to the CODEC(s) is called the CORB engine. The
DMA engine dedicated to transporting responses from the CODEC(s) to the Response
Input Ring Buffer in memory is called the RIRB engine. Every command sent to a
CODEC yields a response from that CODEC. Some commands are “broadcast” type
commands in which case a response will be generated from each CODEC. A CODEC
may also be programmed to generate unsolicited responses, which the RIRB engine
also processes. The platform also supports Programmed IO-based Immediate
Command/Response transport mechanism that can be used by BIOS prior to memory
initialization.
engines. The DMA engine dedicated to transporting commands from the Command
Output Ring Buffer (CORB) in memory to the CODEC(s) is called the CORB engine. The
DMA engine dedicated to transporting responses from the CODEC(s) to the Response
Input Ring Buffer in memory is called the RIRB engine. Every command sent to a
CODEC yields a response from that CODEC. Some commands are “broadcast” type
commands in which case a response will be generated from each CODEC. A CODEC
may also be programmed to generate unsolicited responses, which the RIRB engine
also processes. The platform also supports Programmed IO-based Immediate
Command/Response transport mechanism that can be used by BIOS prior to memory
initialization.
20.1
Signal Descriptions
Please see
for additional details.
The signal description table has the following headings:
•
Signal Name: The name of the signal/pin
•
Direction: The buffer direction can be either input, output, or I/O (bidirectional)
•
Platform Power: The reference power plane.
•
Description: A brief explanation of the signal’s function
The signals in the table above are all muxed and maybe used by other functions.
Table 221. Signals
Signal Name
Direction
Plat. Power
Description
HDA_RST#
O
VAUD
Intel HD Audio Reset: Master H/W reset to external
Codecs
Codecs
HDA_SYNC
O
VAUD
Intel HD Audio Sync: 48 kHz fixed rate
HDA_CLK
O
VAUD
Intel HD Audio Bit Clock (Output): 24 MHz serial
data clock generated by the Intel HD Audio controller
data clock generated by the Intel HD Audio controller
HDA_SDO
O
VAUD
Intel HD Audio Data Out: Serial TDM data output to
the Codec(s). The serial output is double-pumped for a
bit rate of 48 Mb/s
the Codec(s). The serial output is double-pumped for a
bit rate of 48 Mb/s
HDA_SDI[1:0]
I/O
VAUD
Intel HD Audio Serial Data In[1:0]: Serial TDM data
input from the CODEC(s). The serial input is single-
pumped for a bit rate of 24 Mb/s.
input from the CODEC(s). The serial input is single-
pumped for a bit rate of 24 Mb/s.
HDA_LPE_RCOMP
O
Impedance/ current Compensation Output.