Intel E3815 FH8065301567411 Data Sheet

 

Intel

®

 Atom™ Processor E3800 Product Family

Datasheet

2839

PISR

Default: 0000000000000000h

8

0b

RW

Reserved

7

0b

RO

Reserved

6

0b

RW

1 =) Select 25 Mhz clock for the SSP2 base clock; 0 =) Select 19.2 

Mhz clock for the SSP base clock

5

0b

RW

1 =) Select 25 Mhz clock for the SSP1 base clock; 0 =) Select 19.2 

Mhz clock for the SSP base clock

4

0b

RW

1 =) Select 25 Mhz clock for the SSP0 base clock; 0 =) Select 19.2 

Mhz clock for the SSP base clock

3

0b

RO

Satus bit when set to '1 indicates that LPE core is stalled.

2

0b

RW

When set to '1, LPE core is stalled.

1

0b

RW

When set to '1, LPE core boots from the Alternate reset vector. This is 

set to ff2c_0000 - first address of Audio IRAM. Default reset vector is set to 0x100000. 

This needs to be set to 1'b1 for TNG.

0

1b

RW

LPE Reset. LPE held in reset state until this bit is set to 1. Minimum number 

of cycles is defined LPE manual. The bit should be cleared to bring the LPE out of reset.

Memory Mapped I/O Register

(Size: 64 bits)

PCI Configuration Register (Size: 32 bits)

[B:0, D:21, F:0] + 10h

6

3

6

0

5

6

5

2

4

8

4

4

4

0

3

6

3

2

2

8

2

4

2

0

1

6

1

2

8

4

0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RS

VD0

PIS

_

DM

A1

PIS

_

DM

A0

RS

VD

RS

VD1

RS

VD

RS

VD

RS

VD

RS

VD

RS

VD

RS

VD

RS

VD

RS

VD

RS

VD2

63:32

0b

RO

Reserved

31:24

00000000b

RW/1C

DMA 1 interrupts

23:16

00000000b

RW/1C

DMA 0 interrupts

15

0b

RO

Reserved.