Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
284
Datasheet
31
28
24
20
16
12
8
4
0
0 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0
CK
ED
LY
Rsvd_27_2
6_D
T
R
0
PM
EDL
Y
Rsvd_2
3_D
T
R
0
tZ
Qope
r
Rsvd
_11
tZQCS
Rsvd_1
9_D
T
R
0
tX
S
D
LL
Rsvd_1
7_D
T
R
0
tXS
Rsvd_1
5_D
T
R
0
tC
L
tR
C
D
tRP
Rsvd_3_
2_D
T
R
0
DFREQ
Bit
Range
Default &
Access
Field Name (ID): Description
31:28
4h
RW
CKEDLY:
Additional delay between CK/CKB start and SRX command. This delay is
needed for clock to stabilize to meet JEDEC requirements. Delay is CKEDLY multiples of
256 DRAM Clocks. 0ns to 9,600ns (DDR3-800) 0ns to 7,200ns (DDR3-1066)
27:26
0h
RO
Rsvd_27_26_DTR0:
Reserved
25:24
3h
RW
PMEDLY:
The delay, in DRAM clocks, between SR Entry command and Power-Mode
message to DDRIO. 0h - 6 DRAM Clocks 1h - 8 DRAM Clocks 2h - 10 DRAM Clocks 3h -
12 DRAM Clocks
23
0h
RO
Rsvd_23_DTR0:
Reserved
22
0h
RW
tZQoper:
The delay, in DRAM clocks, between ZQC-Long command to any command.
Note: ZQCL command during DRAM Init flow requires longer latency which is controlled
be BIOS. 0h - 256 DRAM Clocks 1h - 384 DRAM Clocks
21
0h
RO
Rsvd_11:
Reserved
20
0h
RW
tZQCS:
The delay, in DRAM clocks, between a ZQC-Short command to any command.
0h - 64 DRAM Clocks 1h - 96 DRAM Clocks
19
0h
RO
Rsvd_19_DTR0:
Reserved
18
0h
RW
tXSDLL:
The delay, in DRAM clocks, between SRX command to any command requiring
locked DLL. Only ZQCL can be sent before tXSDLL is done. 0h - tXS + 256 DRAM Clocks
1h - tXS + 384 DRAM Clocks
17
0h
RO
Rsvd_17_DTR0:
Reserved
16
0h
RW
tXS:
The delay, in DRAM clocks, between SRX command to command not requiring
locked DLL. The Dunit can send a ZQCL command after tXS. JEDEC defines MAX(5CK,
tRFC(min)+10ns) so both values take safety margin. 0h - 256 DRAM Clocks 1h - 384
DRAM Clocks
15
0h
RO
Rsvd_15_DTR0:
Reserved
14:12
1h
RW
tCL:
CAS Latency. Specifies the delay, in DRAM clocks, between the issue of a RD
command and the return of valid data on the DQ bus. 0h - 5 DRAM Clocks (DDR3-800)
1h - 6 DRAM Clocks (DDR3-800, 1066. LPDDR2-800) 2h - 7 DRAM Clocks (DDR3-1066,
1333) 3h - 8 DRAM Clocks (DDR3-1066, 1333, 1600. LPDDR2-1066) 4h - 9 DRAM
Clocks (DDR3-1333, 1600) 5h - 10 DRAM Clocks (DDR3-1333, 1600. LPDDR3-1333) 6h
- 11 DRAM Clocks (DDR3-1600) 7h - Reserved