Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
2869
21.12.4
SSP Interupt Test Register (SSITR)—Offset Ch
The read-write SSP Interrupt Test registers should be used only for testing purposes.
Writing a 1 to the test transmit FIFO request SSITR.TTFS, bit 5, will generate a non-
maskable Interrupt strobe signal to the Interrupt controller, and a DMA request for the
Transmit FIFO. Writing a 1 to the test receive FIFO request SSITR.TRFS, bit 6, will
generate a non-maskable Interrupt strobe signal to the Interrupt controller, and a DMA
request for the Receive FIFO. Writing a 1 to the test receive FIFO overrun bit
SSITR.TROR, bit 7, will generate a non-maskable Interrupt strobe signal to the
Interrupt controller only, no DMA request will be made. Setting any of these bits will
also cause the corresponding status bit(s) to be set in the Enhanced SSP Status
register (SSSR). The Interrupt and/or service request, caused by the setting of one of
these test bits, will remain active until the test bit is cleared by writing a 0 it. Note that
Writes to reserved bits must be zeroes, and Read value of these bits are undetermined.
Access Method
Default: 00000000h
21.12.5
SSP Data Register (SSDR)—Offset 10h
The Enhanced SSP Data registers are single address locations that Read-Write data
transfers can access. The SSDR represents two physical registers: the first is temporary
storage for data on its way out through the Transmit FIFO, the other is temporary
storage for data coming in through the Receive FIFO. As the system accesses the
1:0
00b
RO
RSVD3:
Reserved
Bit
Range
Default &
Access
Description
Type:
Memory Mapped I/O Register
(Size: 32 bits)
BAR Type:
PCI Configuration Register (Size: 32 bits)
BAR Reference:
[B:0, D:21, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RS
VD1
TR
O
R
TR
FS
TT
FS
RS
VD2
Bit
Range
Default &
Access
Description
31:8
000000h
RO
RSVD1:
Reserved
7
0b
RW
Test Receive FIFO overrun (TROR):
0 = No receive FIFO overrun service request 1 =
Generates non-maskable interrupt to CPU. No DMA request is generated
6
0b
RW
Test Receive FIFO service request (TRFS):
0 = No receive FIFO service request 1 =
Generates non-maskable interrupt to CPU and a DMA request for receive FIFO
5
0b
RW
Test Transmit FIFO service request (TTFS):
0 = No transmit FIFO service request
pending 1 = Generates non-maskable interrupt to CPU and a DMA request for transmit
FIFO
4:0
00000b
RO
RSVD2:
Reserved