Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
357
Default: 00000000h
Type:
Message Bus Register
(Size: 32 bits)
Offset:
Op Codes:
h - Read, h - Write
h - Read, h - Write
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
EC
C_
E
N
DUA
L_CH
_
DIS
EFF_E
C
C_EN
EFF_DUA
L_CH_EN
Re
se
rv
ed
_
9
BIOS
_
PDM
D
FX_PDM_
MODE
Re
se
rv
ed
_
6
D
D
RIO_PWRG
A
T
E
GF
X
_
TU
R
B
O_D
ISAB
LE
Re
se
rv
ed
_
4
PCIE_PLL
OFFO
K_EN
US
B_CA
CH
ING_E
N
Bit
Range
Default &
Access
Field Name (ID): Description
31
0h
RW
ECC_EN:
Setting this bit allows using a fused Dual Channel part as a single channel part
with the second Channel being used for ECC.
30
0h
RW
DUAL_CH_DIS:
Setting this bit allows using a fused Dual Channel part as a single
Channel part.
29
0h
RW
EFF_ECC_EN:
Effective ECC Status bit indicating if ECC is enabled(1) or disabled(0)
based on the Fuse and the Downbin bit
28
0h
RW
EFF_DUAL_CH_EN:
Effective Dual Channel Status bit indicating if Dual Channel is
enabled(1) or Single Channel is enabled(0)
27:18
0h
RW
Reserved_9:
Unused, reserved for future use.
17
0h
RW
DFX_POWERGATING (BIOS_PDM):
0: Power Save Mode- Powergate DFX for power
savings 1: PERF_MODE or PDM_MODE: Leave DFX blocks powered up BIOS must always
set this bit before BIOS_RESET_CPL[1:0] bits are set. BYT-M and BYT-D segments leave
DFX Powered up. BYT-T segments provide user option to leave DFX powered up or
powered down. BIOS can change the DFX_Powergating bit to 0 to powergate DFX.
16
0h
RW
DFX_PDM_MODE:
This bit has effect only when DFX_Powergating (bit 17) is set. 0:
PERF_MODE: Access to Performance Counters for SOCHAPs, Memory Traffic etc. 1:
PDM_MODE: Memory BW counts not available but PDM debug messages are available
15:9
0h
RW
Reserved_6:
Reserved
8
0h
RW
DDRIO_PWRGATE:
Firmware sets bit 8 by default to disable ddrio powergating in
S0i3. If BIOS writes to this BYTE, it must set bit 8 to avoid clobbering firmware update.
DDRIO_PWRGATE is not supported on VLV. This bit is relevant only for SKUs supporting
S0i3.
7
0h
RW
GFX_TURBO_DISABLE:
Setting this bit will disable GFX TURBO, even if the Fuses
enable it. Setting this bit is not recommended for VLV
6:2
0h
RW
Reserved_4:
Unused, reserved for future use.
1
0h
RW
PCIE_PLLOFFOK_EN:
When set, P unit will inform PCIE when the last core is entering
and when the first core is exiting PC7 so that PCIE can turn off PLL
0
0h
RW
USB_CACHING_EN:
When set, P unit will inform USB when the last core is entering
and first core is exiting PC7 so that USB caching can be enabled. BIOS will set this bit in
synch with USB caching enable/disable setting. P unit will do the above handshake if the
bit is set, or will skip the handshake if the bit is not set.