Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
400
Datasheet
13.6.50
PUNIT_GPU_FREQ_STS—Offset D8h
Punit GPU Frequency Status Register
Access Method
Default: 00000000h
13.6.51
DPTF_TELB—Offset 108h
Thermal Enforcement Limits for Bandwidth Trips. Write to this Register also triggers
Punit to take action to execute. In the RTL the register is listed as MMIO_SPARE4
Access Method
Default: 00000000h
Type:
Message Bus Register
(Size: 32 bits)
Offset:
Op Codes:
h - Read, h - Write
h - Read, h - Write
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RESE
RVE
D
_7
ST
A
T
US
FREQID
CZ_C
LK
_FREQ
RESE
RVE
D
_4
G
PLLE
NABLE
RESE
RVE
D
_2
GE
NFRE
QS
TA
TU
S
Bit
Range
Default &
Access
Field Name (ID): Description
31:16
0h
RO
RESERVED_7:
Reserved for future use
15:8
0h
RO
STATUSFREQID:
Frequency Encoding for the Frequency Reached
7:6
0h
RO
CZ_CLK_FREQ:
CZ clock Freq encoding is as follows: 00 = 800, 01=1066, 10=1333,
11=Invalid
5
0h
RO
RESERVED_4:
Reserved for future use
4
0h
RO
GPLLENABLE:
0=graphics clocks not from GPLL...1=graphics clocks from GPLL...
3:1
0h
RO
RESERVED_2:
Reserved for future use
0
0h
RO
GENFREQSTATUS:
Status Register bit to be optionally used by Graphics Driver. This bit
Indicates that frequency change is in progress
Type:
Message Bus Register
(Size: 32 bits)
Offset:
Op Codes:
h - Read, h - Write
h - Read, h - Write