Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
PCU – iLB – Real Time Clock (RTC)
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
4545
The hour is represented in twelve or twenty-four hour format, and data can be
represented in BCD or binary format. The design is meant to be functionally compatible
with the Motorola MS146818B. The time keeping comes from a 32.768 kHz oscillating
source, which is divided to achieve an update every second. The lower 14 bytes on the
lower RAM block have very specific functions. The first ten are for time and date
information. The next four (0Ah to 0Dh) are registers, which configure and report RTC
functions. A host-initiated write takes precedence over a hardware update in the event
of a collision.
represented in BCD or binary format. The design is meant to be functionally compatible
with the Motorola MS146818B. The time keeping comes from a 32.768 kHz oscillating
source, which is divided to achieve an update every second. The lower 14 bytes on the
lower RAM block have very specific functions. The first ten are for time and date
information. The next four (0Ah to 0Dh) are registers, which configure and report RTC
functions. A host-initiated write takes precedence over a hardware update in the event
of a collision.
36.2.1
Update Cycles
An update cycle occurs once a second, if the B.SET bit is not asserted and the divide
chain is properly configured. During this procedure, the stored time and date are
incremented, overflow checked, a matching alarm condition is checked, and the time
and date are rewritten to the RAM locations. The update cycle starts at least 488 us
after A.UIP is asserted, and the entire cycle does not take more than 1984 us to
complete. The time and date RAM locations (00h to 09h) are disconnected from the
external bus during this time.
chain is properly configured. During this procedure, the stored time and date are
incremented, overflow checked, a matching alarm condition is checked, and the time
and date are rewritten to the RAM locations. The update cycle starts at least 488 us
after A.UIP is asserted, and the entire cycle does not take more than 1984 us to
complete. The time and date RAM locations (00h to 09h) are disconnected from the
external bus during this time.
36.3
Interrupts
The real-time clock interrupt is internally routed within the SoC both to the I/O APIC
and the 8259. It is mapped to interrupt vector 8. This interrupt does not leave the SoC,
nor is it shared with any other interrupt. IRQ8# from the ILB_LPC_SERIRQ stream is
ignored. However, the High Performance Event Timers can also be mapped to IRQ8#;
in this case, the RTC interrupt is blocked.
and the 8259. It is mapped to interrupt vector 8. This interrupt does not leave the SoC,
nor is it shared with any other interrupt. IRQ8# from the ILB_LPC_SERIRQ stream is
ignored. However, the High Performance Event Timers can also be mapped to IRQ8#;
in this case, the RTC interrupt is blocked.
36.3.1
Lockable RAM Ranges
The RTC battery-backed RAM supports two 8-byte ranges that can be locked: the RC.UL
and RC.LL register bits. When the locking bits are set, the corresponding range in the
RAM is not readable or writable. A write cycle to those locations will have no effect. A
read cycle to those locations will not return the location’s actual value (resultant value
is undefined).
and RC.LL register bits. When the locking bits are set, the corresponding range in the
RAM is not readable or writable. A write cycle to those locations will have no effect. A
read cycle to those locations will not return the location’s actual value (resultant value
is undefined).
Once a range is locked, the range can be unlocked only by a hard reset, which will
invoke the BIOS and allow it to re-lock the RAM range.
invoke the BIOS and allow it to re-lock the RAM range.
36.3.2
Clearing Battery-Backed RTC CMOS RAM
Clearing CMOS RAM in an SoC-based platform can be done by using a jumper on
ILB_RTC_TEST# or a GPI. Implementations should not attempt to clear CMOS by using
a jumper to pull RTC_VCC low.
ILB_RTC_TEST# or a GPI. Implementations should not attempt to clear CMOS by using
a jumper to pull RTC_VCC low.
Note:
The entire Extended Bank and bytes 0Eh-7Fh of the Standard Bank will be cleared.