Intel E3815 FH8065301567411 Data Sheet

Intel

®

 Atom™ Processor E3800 Product Family

4556

Datasheet

Counter 0 Interval Time Status Byte Format.Status byte can be read following a Read 

Back Command. If latch status is chosen (bit 4=0, Read Back Command) as a read 

back option for counter 0, the next read from this register returns the status byte.

Default: 00h

40h

1

00h

41h

1

00h

42h

1

00h

43h

1

00h

50h

1

00h

51h

1

00h

52h

1

00h

61h

1

20h

I/O Register

(Size: 8 bits)

7

4

0

0

0

0

0

0

0

0

0

CS

CR

RW

S

MD

CT

7

0b

RO

Counter State (CS): When set, OUT of the counter is set. When cleared, OUT of the 

counter is 0.

6

X

RO

Count Register: When cleared, indicates when the last count written to the Count 

Register (CR) has been loaded into the counting element (CE) and is available for 

reading. The time this happens depends on the counter mode.

5:4

X

RO

Read/Write Selection: These reflect the read/write selection made through 

bits[5:4] of the control register. The binary codes returned during the status read match 

the codes used to program the counter read/write selection. 00 Counter Latch 

Command 01 Read/Write Least Significant Byte (LSB) 10 Read/Write Most Significant 

Byte (MSB) 11 Read/Write LSB then MSB

3:1

X

RO

Mode: Returns the counter mode programming. The binary code returned matches 

the code used to program the counter mode, as listed under the bit function above. Bits 

Mode Description 000 0 Out signal on end of count (=0) 001 1 Hardware retriggerable 

one-shot x10 2 Rate generator (divide by n counter) x11 3 Square wave output 100 4 

Software triggered strobe 101 5 Hardware triggered strobe

0

X

RO

Countdown Type: 0 for binary countdown or a 1 for binary coded decimal (BCD) 

countdown.