Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
4564
Datasheet
38.5
PCU iLB High Performance Event Timer (HPET) Memory
Mapped IO Registers
38.5.1
GCID (HPET_GCID)—Offset FED00000h
General Capabilities and ID
Access Method
Default: 0429B17F8086A201h
Table 335.
Summary of PCU iLB High Performance Event Timer (HPET) Memory Mapped
I/O Registers—
Offset
Size
Register ID—Description
Default Value
FED00000h
8
0429B17F8086A201h
FED00010h
8
0000000000000000h
FED00020h
8
0000000000000000h
FED000F0h
8
0000000000000000h
FED00100h
8
00F0000000000030h
FED00108h
4
FFFFFFFFh
FED0010Ch
4
FFFFFFFFh
FED00120h
8
00F0000000000000h
FED00128h
8
00000000FFFFFFFFh
FED00140h
8
00F0080000000000h
FED00148h
8
00000000FFFFFFFFh
Type:
Memory Mapped I/O Register
(Size: 64 bits)
6
3
6
0
5
6
5
2
4
8
4
4
4
0
3
6
3
2
2
8
2
4
2
0
1
6
1
2
8
4
0
0 0 0 0 0 1 0 0 0 0 1 0 1 0 0 1 1 0 1 1 0 0 0 1 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0 0 1
CTP
VID
LRC
RES
E
RVE
D
CS
NT
RID
Bit
Range
Default &
Access
Description
63:32
0429B17Fh
RO
CTP:
Counter Tick Period (CTP): Indicates a period of 69.841279ns, (14.1318 MHz clock
period)
31:16
8086h
RO
VID:
Vendor ID (VID): Value of 8086h indicates Intel.
15
1b
RO
LRC:
Legacy Rout Capable (LRC): Indicates support for Legacy Interrupt Rout.
14
0b
RO
RESERVED:
Reserved.
13
1b
RO
CS:
Counter Size (CS): This bit is set to indicate that the main counter is 64 bits wide.